View GMS87C1202_6125094.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8-bit single-chip microcontrollers gms81c1102 gms81c1202 users manual jan. 2002 ver 2.0
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 1. overview ................................................................................................................... .... 1 1.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. block diagram(gms81c1202) .................................................................................. 2 3. pin assignment(gms81c1202) .................................................................................. 2 4. block diagram(gms81c1102) .................................................................................. 3 5. pin assignment(gms81c1102) .................................................................................. 3 6. package dimension(gms81c1202) .......................................................................... 4 7. package dimension(gms81c1102) .......................................................................... 5 8. pin function ............................................................................................................... .. 6 9. port structures ....................................................................................................... 7 10. electrical characteristics -gms81c1102, gms81c1202 .......................... 10 10.1 absolute maximum ratings - gms81c1102, gms81c1202 . . . . . . . . . . . . . . . . 10 10.2 recommended operating conditions - gms81c1102, gms81c1202 . . . . . . . . . 10 10.3 dc electrical characteristics - gms81c1102, gms81c1202 . . . . . . . . . . . . . . . . 11 10.4 a/d converter characteristics - gms81c1102, gms81c1202 . . . . . . . . . . . . . . . 13 10.5 ac characteristics - gms81c1102, gms81c1202 . . . . . . . . . . . . . . . . . . . . . . . 14 10.6 typical characteristics - gms81c1102, gms81c1202 . . . . . . . . . . . . . . . . . . . . 15 11. electrical characteristics - gms87c1102, GMS87C1202 ......................... 19 11.1 absolute maximum ratings - gms87c1102, GMS87C1202 . . . . . . . . . . . . . . . . 19 11.2 recommended operating conditions - gms87c1102, GMS87C1202 . . . . . . . . . 19 11.3 dc electrical characteristics - gms87c1102, GMS87C1202 . . . . . . . . . . . . . . . . 20 11.4 a/d converter characteristics - gms87c1102, GMS87C1202 . . . . . . . . . . . . . . . 21 11.5 ac characteristics - gms87c1102, GMS87C1202 . . . . . . . . . . . . . . . . . . . . . . . 22 11.6 typical characteristics - gms87c1102, GMS87C1202 . . . . . . . . . . . . . . . . . . . . 23 12. memory organization ......................................................................................... 26 12.1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 12.2 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 12.3 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12.4 addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 13. i/o ports ................................................................................................................. ... 38 13.1 ra and raio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 13.2 rb and rbio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13.3 rc and rcio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 14. clock generator ................................................................................................. 41 14.1 oscillation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 15. basic interval timer ........................................................................................... 43 16. timer / counter ...................................................................................................... 44 16.1 8-bit timer/counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 16.2 16-bit timer/counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16.3 8-bit compare output ( 16-bit ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16.4 8-bit capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 16.5 16-bit capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 16.6 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 17. buzzer output function .................................................................................... 53 18. analog to digital converter .......................................................................... 54 19. interrupts ............................................................................................................... 5 7 19.1 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 19.2 brk interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 19.3 multi interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 19.4 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 20. watchdog timer .................................................................................................... 62 21. power saving mode .............................................................................................. 63 22. reset ..................................................................................................................... ..... 68 23. power fail processor ........................................................................................ 69 24. otp programming .................................................................................................. 71 appendix instruction map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 1 gms81c1102 / gms81c1202 cmos single-chip 8-bit microcontroller 1. overview 1.1 description the gms81c1102 and gms81c1202 are an advanced cmos 8-bit microcontroller with 2k bytes of rom. the hynix gms81c1102 and gms81c1202 are a powerful microcontroller which provides a highly flexible and cost effective solution to many small applications. the gms81c1102 and gms81c1202 provide the following standard features: 2k bytes of rom, 128 bytes of ram, 8-bit timer/counter, 8-bit a/d converter, 10-bit high speed pwm output, programmable buzzer driving port (gms81c1202 only), on-chip oscillator and clock circuitry. in addition, the gms81c1102 and gms81c1202 support power saving modes to reduce power consumption. this document is only explained for the base of gms81c1202, the eliminated functions are same as below. 1.2 features ? 2k bytes on-chip program memory ? 128 bytes of on-chip data ram ? minimum instruction execution time: - 500ns at 8mhz (2cycle nop instruction) ? 2.2v to 6.0v wide operating range ? basic interval timer ? two 8-bit timer/ counters ? 10-bit high speed pwm output ? two external interrupt ports (gms81c1102 has one external interrupt port) ? one programmable buzzer driving port (gms81c1202 only) ? 15 programmable i/o lines (gms81c1102 has 11 programmable i/o lines) ? seven interrupt sources (gms81c1102 has six interrupt sources) ? 8-channel 8-bit on-chip analog to digital con- verter ? watch dog timer ? oscillation : - crystal - ceramic resonator - external oscillator - rc oscillation ? power down mode - stop mode - wake-up timer mode - rc-wdt mode ? power fail processor ( noise immunity circuit ) 1.3 development tools the gms800 family is supported by a full-featured macro assembler, an in-circuit emulators choice-dr.?, and add-on board type otp writer dr.writer? . the availability of otp devices is especially useful for customers expecting frequent code changes and updates. the otp devices, packaged in plastic packages, permit the user to program them once. device name rom size ram size i/o buz int1 package gms81c1102 2k bytes 128 bytes 11 no no 16dip/sop gms81c1202 2k bytes 128 bytes 15 yes yes 20dip/sop gms87c1102 2k bytes(otp) 128 bytes 11 no no 16dip/sop GMS87C1202 2k bytes(otp) 128 bytes 15 yes yes 20dip/sop in circuit emulator choice-dr. assembler hynix semiconductor macro assembler otp writer dr.writer
gms81c1102 / gms81c1202 2 jan. 2002 ver 2.0 2. block diagram(gms81c1202) 3. pin assignment(gms81c1202) alu accumulator stack pointer interrupt controller data memory 8-bit converter a/d 8-bit counter timer/ program memory data table pc 8-bit basic timer interval watch-dog timer instruction ra rb rc buzzer driver psw system controller timing generator system clock controller clock generator reset xin xout ra0 / ec0 ra1 / an1 ra2 / an2 ra3 / an3 ra4 / an4 ra5 / an5 ra6 / an6 ra7 / an7 rb0 / an0 / avref rb1 / buz rb2 / int0 rb3 / int1 rb4 / cmp0 / pwm rc0 rc1 v dd v ss power supply decoder high pwm speed 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ra3 / an3 ra2 / an2 ra1 / an1 ra0 / ec0 rc1 rc0 v ss reset xout xin an4 / ra4 an5 / ra5 an6 / ra6 an7 / ra7 v dd an0 / avref / rb0 buz / rb1 int0 / rb2 int1 / rb3 pwm / comp0 / rb4 ra3 / an3 ra2 / an2 ra1 / an1 ra0 / ec0 rc1 rc0 v ss reset xout xin an4 / ra4 an5 / ra5 an6 / ra6 an7 / ra7 v dd an0 / avref / rb0 buz / rb1 int0 / rb2 int1 / rb3 pwm / comp0 / rb4 20 dip 20 sop 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 3 4. block diagram(gms81c1102) 5. pin assignment(gms81c1102) alu accumulator stack pointer interrupt controller data memory 8-bit converter a/d 8-bit counter timer/ program memory data table pc 8-bit basic timer interval watch-dog timer instruction ra rb psw system controller timing generator system clock controller clock generator reset xin xout ra0 / ec0 ra1 / an1 ra2 / an2 ra3 / an3 ra4 / an4 ra5 / an5 ra6 / an6 ra7 / an7 rb0 / an0 / avref rb2 / int0 rb4 / cmp0 / pwm v dd v ss power supply decoder high pwm speed 1 2 3 4 5 6 7 8 9 10 16 15 14 13 12 11 ra3 / an3 ra2 / an2 ra1 / an1 ra0 / ec0 v ss reset xout xin an4 / ra4 an5 / ra5 an6 / ra6 an7 / ra7 v dd an0 / avref / rb0 int0 / rb2 pwm / comp0 / rb4 ra3 / an3 ra2 / an2 ra1 / an1 ra0 / ec0 v ss reset xout xin an4 / ra4 an5 / ra5 an6 / ra6 an7 / ra7 v dd an0 / avref / rb0 int0 / rb2 pwm / comp0 / rb4 16 dip 16 sop 1 2 3 4 5 6 7 89 10 16 15 14 13 12 11
gms81c1102 / gms81c1202 4 jan. 2002 ver 2.0 6. package dimension(gms81c1202) 26.2 0.3 0.46 0.07 1.45 0.2 typ 2.54 typ 7.62 6.54 0.3 0.25 0.05 0 ~ 15 max 4.57 min 0.38 3.3 0.25 7.5 0.1 10.35 0.2 12.8 0.2 2.5 0.15 0.42 0.08 typ 1.27 0.2 0.1 0.26 0.05 0 ~ 8 0.7 0.3 20 dip 20 sop unit : mm
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 5 7. package dimension(gms81c1102) 19.2 0.2 0.46 0.07 1.45 0.2 typ 2.54 typ 7.62 6.3 0.3 0.25 0.05 0 ~ 15 max 4.32 min 0.38 3.3 0.25 7.5 0.1 10.35 0.2 10.25 0.05 2.5 0.15 0.42 0.08 typ 1.27 0.18 0.05 0.27 0.04 0 ~ 8 0.7 0.3 16 dip 16 sop unit : mm 0.75 0.3
gms81c1102 / gms81c1202 6 jan. 2002 ver 2.0 8. pin function v dd : supply voltage. v ss : circuit ground. reset : reset the mcu. x in : input to the inverting oscillator amplifier and input to the internal clock operating circuit. x out : output from the inverting oscillator amplifier. if rc option is used, the oscillator frequency divided by 4 (xin/4) comes out from xout pin. ra0~ra7 : ra is an 8-bit, cmos, bidirectional i/o port. ra pins can be used as outputs or inputs according to 1 or 0 written in the port direction register(raio). in addition, ra serves the functions of the various special features in table 8-1. rb0~rb4 : rb is a 5-bit, cmos, bidirectional i/o port. rb pins can be used as outputs or inputs according to 1 or 0 written in the port direction register(rbio). rb serves the functions of the various following special features. rc0~rc1 : rc is a 2-bit, cmos, bidirectional i/o port. rc pins can be used as outputs or inputs according to 1 or 0 written in the port direction register(rcio) . port pin alternate function ra0 ra1 ra2 ra3 ra4 ra5 ra6 ra7 ec0 ( event counter input source ) an1 ( analog input port 1 ) an2 ( analog input port 2 ) an3 ( analog input port 3 ) an4 ( analog input port 4 ) an5 ( analog input port 5 ) an6 ( analog input port 6 ) an7 ( analog input port 7 ) table 8-1 ra port port pin alternate function rb0 rb1 rb2 rb3 rb4 an0 ( analog input port 0 ) avref ( external analog reference pin ) buz ( buzzer driving output port ) int0 ( external interrupt input port 0 ) int1 ( external interrupt input port 1 ) pwm ( pwm output ) comp0 ( timer0 compare output ) table 8-2 rb port pin name pin no. in/out function v dd 5 - supply voltage v ss 14 - circuit ground reset 13 i reset signal input x in 11 i x out 12 o ra0 (ec0) 17 i/o (input) 8-bit general i/o ports external event counter input ra1 (an1) 18 i/o (input) analog input port 1 ra2 (an2) 19 i/o (input) analog input port 2 ra3 (an3) 20 i/o (input) analog input port 3 ra4 (an4) 1 i/o (input) analog input port 4 ra5 (an1) 2 i/o (input) analog input port 5 ra6 (an1) 3 i/o (input) analog input port 6 ra7 (an7) 4 i/o (input) analog input port 7 rb0 (avref/an0) 6 i/o (input) 5-bit general i/o ports analog input port 0 / analog reference rb1 (buz) 7 i/o (output) buzzer driving output rb2 (int0) 8 i/o (input) external interrupt input 0 rb3 (int1) 9 i/o (input) external interrupt input 1 rb4 (pwm/comp0) 10 i/o (output/output) pwm output or timer compare output rc0 15 i/o 2-bit general i/o ports rc1 16 i/o table 8-3 pin description
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 7 9. port structures ? reset ? xin, xout ? ra0/ec0 v ss internal reset v dd v ss xout xin rc option fxin ? 4 stop to system clk v dd 0 1 data bus data bus data bus data reg. direction reg. read ec0
gms81c1102 / gms81c1202 8 jan. 2002 ver 2.0 ? ra1/an1 ~ ra7/an7 ? rb0 / an0 / avref v dd v ss data bus data bus data bus read to a/d converter analog input mode (ansel7 ~ 1) analog ch. selection (adcm.4 ~ 2) data reg. direction reg. v dd v ss data bus data bus data bus read to a/d converter analog input mode (ansel0) analog ch0 selection (adcm.4 ~ 2) avrefs avrefs internal v dd 0 1 to vref of a/d data reg. direction reg.
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 9 ? rb1/buz, rb4/pwm0/comp ? rb2/int0, rb3/int1 ? rc0, rc1 v dd v ss data bus data bus data bus read 0 1 function select pwm/comp buz data reg. direction reg. v dd v ss data bus data bus data bus read function select pull-up select int0 int1 schmitt trigger weak pull-up data reg. direction reg. v dd v ss data bus data bus data bus read data reg. direction reg.
gms81c1102 / gms81c1202 10 jan. 2002 ver 2.0 10. electrical characteristics -gms81c1102, gms81c1202 10.1 absolute maximum ratings - gms81c1102, gms81c1202 supply voltage ........................................... -0.3 to +6.5 v storage temperature ................................-40 to +125 c voltage on any pin with respect to ground (v ss ) ............................................................... -0.3 to v dd +0.3 maximum current out of v ss pin ........................200 ma maximum current into v dd pin ..........................150 ma maximum current sunk by (i ol per i/o pin) ........25 ma maximum output current sourced by (i oh per i/o pin) ...............................................................................15 ma maximum current ( s i ol ) .................................... 150 ma maximum current ( s i oh ).................................... 100 ma note: stresses above those listed under "absolute maxi- mum ratings" may cause permanent damage to the device. this is a stress rating only and functional op- eration of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 10.2 recommended operating conditions - gms81c1102, gms81c1202 parameter symbol condition specifications unit min. max. supply voltage v dd f xin =8mhz 4.5 6.0 v f xin =4.2mhz 2.2 6.0 operating frequency f xin v dd =4.5~6.0v 18 mhz v dd =2.2~6.0v 14.2 operating temperature t opr -20 85 c
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 11 10.3 dc electrical characteristics - gms81c1102, gms81c1202 ? (v dd =4.5~6.0v, v ss =0v, f xin =1mhz~8mhz, t a =-20 c~+85 c) parameter symbol pin 1 1. rc0, rc1, rb1 and rb3 pins are applied for gms81c1202 only. test condition specification unit min typ 2 2. data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max input high voltage v ih1 x in, reset v dd =4.5~6.0v 0.8v dd v dd v v ih2 rb2, rb3 0.8v dd v dd v ih3 ra,rb0,rb1,rb4,rc 0.7v dd v dd input low voltage v il1 x in, reset v dd =4.5~6.0v 0 0.2v dd v v il2 rb2, rb3 0 0.2v dd v il3 ra,rb0,rb1,rb4,rc 0 0.3v dd output high voltage v oh ra, rb, rc v dd = 5v, i oh = -2ma v dd -1 v output low voltage v ol ra, rb, rc v dd = 5v, i ol = 10ma 1v input leakage current i il reset ,ra,rb,rc v in = v ss ~v dd 5 ua i il x in 20 input pull-up current i pu rb2, rb3 3 3. this parameter is valid when the bit pupselx is selected and set the input mode or interrupt input function. v dd = 5v, v in = v ss -350 -280 -200 ua power fail detect voltage v pfd v dd 23.54v normal operating current i dd v dd v dd =6.0v, f xin =8mhz 46ma wake-up timer mode current i wkup v dd v dd =6.0v, f xin =8mhz 12ma rc-oscillated watchdog timer mode current i rcwdt v dd v dd = 6.0v, f xin = 8mhz 0.6 0.8 ma stop mode current i stop v dd v dd = 6.0v 0.5 2 ua hysteresis v t+ ~ v t- reset , rb2, rb3 0.5 v internal rc oscillation period ( rc-wdt clk ) t rcwdt x out v dd = 5v, f xin = 8mhz 100 200 us rc oscillation frequency ( system clk ) f rcosc 4 4. this parameter is measured in x out pin, and measured frequency is must be 4times to be internal system clock because of this x out signal is divided by 4 of system clock. x out r = 15k w , c=30pf 400 600 khz
gms81c1102 / gms81c1202 12 jan. 2002 ver 2.0 ? (v dd =2.2~6.0v, v ss =0v, f xin =1mhz~4.2mhz, t a =-20 c ~+85 c ) parameter symbol pin 1 1. rc0, rc1, rb1 and rb3 pins are applied for gms81c1202 only. test condition specification unit min typ 2 2. data in typ column is at 3v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max input high voltage v ih1 x in v dd =2.2~6.0v 0.8v dd v dd v v ih2 reset 0.9v dd v dd v ih3 rb2, rb3 0.8v dd v dd v ih4 ra,rb0,rb1,rb4,rc 0.7v dd v dd input low voltage v il1 x in v dd =2.2~6.0v 0 0.2v dd v v il2 reset 0 0.1v dd v il3 rb2, rb3 0 0.2v dd v il4 ra,rb0,rb1,rb4,rc 0 0.3v dd output high voltage v oh ra, rb, rc v dd = 3v, i oh = -2ma 2.5 v output low voltage v ol ra, rb, rc v dd = 3v, i ol = 5ma 0.7 v input leakage current i il reset ,ra,rb,rc v in = v ss ~v dd 5 ua i il x in 15 input pull-up current i pu rb2, rb3 3 3. this parameter is valid when the bit pupselx is selected and set the input mode or interrupt input function. v dd = 3v, v in = v ss -100 -60 -40 ua power fail detect voltage v pfd v dd 23.54v normal operating current i dd v dd v dd = 3v, f xin = 4mhz 23ma wake-up timer mode current i wkup v dd v dd = 3v, f xin = 4mhz 0.5 1 ma rc-oscillated watchdog timer mode current i rcwdt v dd v dd = 3v, f xin = 4mhz 0.3 0.6 ma stop mode current i stop v dd v dd = 3v 0.2 1 ua hysteresis v t+ ~ v t- reset , rb2, rb3 0.5 v internal rc oscillation period ( rc-wdt clk ) t rcwdt x out v dd = 3v, f xin = 4mhz 200 400 us rc oscillation frequency ( system clk ) f rcosc 4 4. this parameter is measured in x out pin, and measured frequency is must be 4times to be internal system clock because of this x out signal is divided by 4 of system clock. x out v dd = 3v, r = 47k w , c=7pf 200 300 khz
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 13 10.4 a/d converter characteristics - gms81c1102, gms81c1202 ? (v ss =0v, v dd =3.072v/@f xin =4mhz, v dd =5.12v/@f xin =8mhz, t a =-20 c~+85 c ) parameter symbol condition specifications unit min. typ. max. analog input voltage range v ain avrefs=0 v ss - v dd v avrefs=1 v ss - v ref analog power supply input voltage range v ref avrefs=1 3 - v dd v overall accuracy n acc - 1.0 1.5 lsb non-linearity error n nle - 0.8 1.2 lsb differential non-linearity error n dnle - 1.0 1.5 lsb zero offset error n zoe - 1.0 1.5 lsb full scale error n fse - 0.25 0.5 lsb gain error n nle - 1.0 1.5 lsb conversion time t conv f xin =4mhz --20 m s f xin =8mhz --10 av ref input current i ref f xin =4mhz -0.40.6 ma f xin =8mhz -0.51.0
gms81c1102 / gms81c1202 14 jan. 2002 ver 2.0 10.5 ac characteristics - gms81c1102, gms81c1202 (t a =-20~+85 c, v dd =5v 10% , v ss =0v) figure 10-1 timing chart parameter symbol pins specifications unit min. typ. max. operating frequency f cp x in 1-8mhz external clock pulse width t cpw x in 50 - - ns external clock transition time t rcp, t fcp x in - - 20 ns external input pulse width t epw int0, int1, ec0 2 - - t sys reset input width t rst reset 8- - t sys t rcp t fcp x in int0, int1 ec0 0.5v v dd -0.5v 0.2v dd reset 0.2v dd 0.8v dd t rst t epw t epw 1/f cp t cpw t cpw t sys
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 15 10.6 typical characteristics - gms81c1102, gms81c1202 this graphs and tables provided in this section are for de- sign guidance only and are not tested or guranteed. in some graphs or tables the data presented are out- side specified operating range (e.g. outside specified v dd range). this is for imformation only and divices are guranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation ta= 25 c ta=25 c i dd - v dd 8 6 4 2 0 (ma) i dd 23 45 6 v dd (v) normal operation 8 6 4 2 0 (mhz) f xin 23 45 6 v dd (v) operating area 4mhz 12 i wkup - v dd 2.0 1.5 1.0 0.5 0 (ma) i dd 23 45 6 v dd (v) wake-up timer mode i rcwdt - v dd 400 300 200 100 0 ( m a) i dd 23 45 6 v dd (v) rc-wdt in stop mode ta=25 c f xin = 8mhz 4mhz f xin = 4/8 mhz 4mhz ta=25 c frequency affects the current so little. 10 i stop - v dd 0.8 0.6 0.4 0.2 0 ( m a) i dd 23 45 6 v dd (v) stop mode 25 c, 125 c ta= - 40 c f xin =8mhz f xin = 8mhz
gms81c1102 / gms81c1202 16 jan. 2002 ver 2.0 i ol - v ol , v dd =5v 16 12 8 4 0 (ma) i ol v ol (v) i oh - v oh , v dd =5v -8 -6 -4 -2 0 (ma) i oh 44.55 v oh (v) 0.20.4 0.60.81.0 -40 c 125 c 25 c -40 c 125 c 25 c 20 i ol - v ol , v dd =3v 12 8 4 0 (ma) i ol v ol (v) 0.20.4 0.60.81.0 125 c -40 c 25 c -10 i oh - v oh , v dd =5v -6 -4 -2 0 (ma) i oh 22.53 v oh (v) -40 c 125 c 25 c -8
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 17 v dd - v ih1 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) v dd - v ih2 4 3 2 1 0 (v) v ih2 23 45 6 v dd (v) 1 x in hysteresis input v dd - v ih4 4 3 2 1 0 (v) v ih4 23 45 6 v dd (v) reset f xin =4mhz v dd - v il1 4 3 2 1 0 (v) v il1 23 45 6 v dd (v) v dd - v il2 4 3 2 1 0 (v) v il2 23 45 6 v dd (v) ta=25 c 1 x in hysteresis input v dd - v il4 4 3 2 1 0 (v) v il4 23 45 6 v dd (v) reset v dd - v ih3 4 3 2 1 0 (v) v ih3 23 45 6 v dd (v) normal input 1 v dd - v il3 4 3 2 1 0 (v) v il3 23 45 6 v dd (v) normal input 1 f xin =4mhz ta=25 c f xin =4mhz ta=25 c f xin =4mhz ta=25 c f xin =4mhz ta=25 c f xin =4mhz ta=25 c f xin =4mhz ta=25 c f xin =4mhz ta=25 c
gms81c1102 / gms81c1202 18 jan. 2002 ver 2.0 table 10-1 rc oscillator frequencies cext rext average fosc @ 5v,25 c 24pf 20k 2.02mhz 14.11% 33k 1.34mhz 11.50% 47k 0.952mhz 10.30% 100k 0.48mhz 9.07% 39pf 20k 1.536mhz 14.79% 33k 1.012mhz 11.67% 47k 0.72mhz 10.42% 100k 0.364mhz 9.75% 100pf 20k 0.78mhz 13.53% 33k 0.512mhz 10.35% 47k 0.364mhz 9.48% 100k 0.18mhz 7.34% typical rc o scillator 1.5 1.0 0.5 0 (mhz) f osc 2.5 3 4 5 6 v dd (v) frequency vs . v dd 2.5 2.0 3.5 4.5 5.5 ta=25 c r=20k r=33k r=47k r=100k typical rc oscillator 1.2 1.0 0.8 0 (m hz) f osc 2.5 3 4 5 6 v dd (v) frequency vs . v dd 1.6 1.4 3.5 4.5 5.5 r=20k r=47k r=100k 0.2 0.4 0.6 r=33k typical rc oscillator 0.6 0.5 0.4 0 (mhz) f osc 2.5 3 4 5 6 v dd (v) frequency vs . v dd 0.8 0.7 3.5 4.5 5.5 r=20k r=47k r=100k 0.1 0.2 0.3 r=33k typical r c o scillator 1.005 1.000 0.995 0.975 f osc 010305070 v dd (v) frequency vs . temperature 1.010 20 40 60 0.980 0.985 0.990 v dd =5v v dd =3v f osc (25 c) cext=24pf ta=25 c cext=39pf ta=25 c cext=100pf r=25k cext=24pf
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 19 11. electrical characteristics - gms87c1102, GMS87C1202 11.1 absolute maximum ratings - gms87c1102, GMS87C1202 supply voltage ........................................... -0.3 to +6.5 v storage temperature ................................-40 to +125 c voltage on any pin with respect to ground (v ss ) ............................................................... -0.3 to v dd +0.3 maximum current out of v ss pin ........................200 ma maximum current into v dd pin ..........................150 ma maximum current sunk by (i ol per i/o pin) ........25 ma maximum output current sourced by (i oh per i/o pin) ...............................................................................15 ma maximum current ( s i ol ) .................................... 150 ma maximum current ( s i oh ).................................... 100 ma note: stresses above those listed under "absolute maxi- mum ratings" may cause permanent damage to the device. this is a stress rating only and functional op- eration of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 11.2 recommended operating conditions - gms87c1102, GMS87C1202 parameter symbol condition specifications unit min. max. supply voltage v dd f xin =8mhz 4.5 5.5 v f xin =4.2mhz 2.7 5.5 operating frequency f xin v dd =4.5~5.5v 18 mhz v dd =2.7~5.5v 14.2 operating temperature t opr -20 85 c
gms81c1102 / gms81c1202 20 jan. 2002 ver 2.0 11.3 dc electrical characteristics - gms87c1102, GMS87C1202 (t a =-20~85 c, v dd =2.7~5.5v , v ss =0v) parameter symbol pin 1 1. rc0, rc1, rb1 and rb3 pins are applied for GMS87C1202 only. test condition specification unit min typ 2 2. data in typ column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. max input high voltage v ih1 x in, reset 0.8v dd v dd v v ih2 rb2, rb3 0.8v dd v dd v ih3 ra,rb0,rb1,rb4,rc 0.7v dd v dd input low voltage v il1 x in, reset 0 0.2v dd v v il2 rb2, rb3 0 0.2v dd v il3 ra,rb0,rb1,rb4,rc 0 0.3v dd output high voltage v oh ra, rb, rc v dd = 5v, i oh = -5ma v dd -1 v output low voltage v ol ra, rb, rc v dd = 5v, i ol = 10ma 1.0 v input high leakage current i ih1 reset ,ra,rb,rc v dd = 5.5v 5 ua i ih2 x in 15 input low leakage current i il1 reset ,ra,rb,rc v dd = 5.5v -5 ua i il2 x in -15 input pull-up current i p rb2, rb3 3 3. this parameter is valid when the bit pupselx is selected and set the input mode or interrupt input function. v dd = 5v -350 -280 -200 ua v dd = 3v -100 -60 -40 power fail detect voltage v pfd v dd v dd = 5v 23.54v normal operating current i dd v dd v dd = 5.5v, f xin = 8mhz 46 ma v dd = 3v, f xin = 4mhz 23 wake-up timer mode current i wkup v dd v dd = 5.5v, f xin = 8mhz 11.8 ma v dd = 3v, f xin = 4mhz 0.5 1 rc-oscillated watchdog timer mode current i rcwdt v dd v dd = 5.5v, f xin = 8mhz 0.6 0.8 ma v dd = 3v, f xin = 4mhz 0.3 0.6 stop mode current i stop v dd v dd = 5.5v, f xin = 8mhz 0.5 2 ua v dd = 3v, f xin = 4mhz 0.2 1 hysteresis v t+ ~ v t- reset , rb2, rb3 0.5 v internal rc oscillation period ( rc-wdt clk ) t rcwdt x out v dd = 5v 100 250 us v dd = 3v 200 500 rc oscillation frequency ( system clk ) f rcosc 4 4. this parameter is measured in x out pin, and measured frequency is must be 4times to be internal system clock because of this x out signal is divided by 4 of system clock. x out v dd = 5v, r = 15k w , c=30pf 400 600 khz v dd = 3v, r = 47k w , c=7pf 200 300
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 21 11.4 a/d converter characteristics - gms87c1102, GMS87C1202 (t a =25 c, v ss =0v, v dd =5.12v @ f xin =8mhz , v dd =3.072v @ f xin =4mhz ) parameter symbol condition specifications unit min. typ. max. analog input voltage range v ain avrefs=0 v ss - v dd v avrefs=1 v ss - v ref analog power supply input voltage range v ref avrefs=1 3 - v dd v overall accuracy n acc - 1.0 1.5 1 1. this parameter is valid in the range from 02h to ffh, and typical value 1.3 lsb, maximum value 2.0 lsb in the other range (from 00h to 01h). lsb non-linearity error n nle - 0.8 1.2 lsb differential non-linearity error n dnle - 1.0 1.5 lsb zero offset error n zoe - 1.3 2.0 lsb full scale error n fse - 0.25 0.5 lsb gain error n nle - 1.0 1.5 lsb conversion time t conv f xin =8mhz --10 m s f xin =4mhz --20 av ref input current i ref avrefs=1 - 0.5 1.0 ma
gms81c1102 / gms81c1202 22 jan. 2002 ver 2.0 11.5 ac characteristics - gms87c1102, GMS87C1202 (t a =-20~+85 c, v dd =5v 10% , v ss =0v) figure 11-1 timing chart parameter symbol pins specifications unit min. typ. max. operating frequency f cp x in 1-8mhz external clock pulse width t cpw x in 50 - - ns external clock transition time t rcp, t fcp x in - - 20 ns oscillation stabilizing time t st x in , x out --20ms external input pulse width t epw int0, int1, ec0 2 - - t sys reset input width t rst reset 8- - t sys t rcp t fcp x in int0, int1 0.5v v dd -0.5v 0.2v dd reset 0.2v dd 0.8v dd ec0 t rst t epw t epw 1/f cp t cpw t cpw t sys
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 23 11.6 typical characteristics - gms87c1102, GMS87C1202 this graphs and tables provided in this section are for de- sign guidance only and are not tested or guranteed. in some graphs or tables the data presented are out- side specified operating range (e.g. outside specified v dd range). this is for imformation only and divices are guranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 s ) and (mean - 3 s ) respectively where s is standard deviation ta= 25 c ta=25 c i dd - v dd 8 6 4 2 0 (ma) i dd 23 45 6 v dd (v) normal operation 8 6 4 2 0 (mhz) f xin 23 45 6 v dd (v) operating area f xin = 8mhz 4mhz 10 i wkup - v dd 2.0 1.5 1.0 0.5 0 (ma) i dd 23 45 6 v dd (v) wake-up timer mode i rcwdt - v dd 20 15 10 5 0 ( m a) i dd 23 45 6 v dd (v) rc-wdt in stop mode ta=25 c f xin = 8mhz 4mhz f xin = 8mhz 4mhz ta=25 c
gms81c1102 / gms81c1202 24 jan. 2002 ver 2.0 i ol - v ol , v dd =5v 40 30 20 10 0 (ma) i ol v ol (v) i oh - v oh , v dd =5v -20 -15 -10 -5 0 (ma) i oh 23 456 v oh (v) 12 345 f xin =4mhz v dd - v ih1 4 3 2 1 0 (v) v ih1 23 45 6 v dd (v) v dd - v ih2 4 3 2 1 0 (v) v ih2 23 45 6 v dd (v) ta=25 c f xin =4khz ta=25 c 1 x in , reset hysteresis input -25 c 85 c 25 c -25 c 85 c 25 c v dd - v ih3 4 3 2 1 0 (v) v ih3 23 45 6 v dd (v) f xin =4khz ta=25 c normal input f xin =4mhz v dd - v il1 4 3 2 1 0 (v) v il1 23 45 6 v dd (v) v dd - v il2 4 3 2 1 0 (v) v il2 23 45 6 v dd (v) ta=25 c f xin =4khz ta=25 c 1 x in , reset hysteresis input v dd - v il3 4 3 2 1 0 (v) v il3 23 45 6 v dd (v) f xin =4khz ta=25 c normal input
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 25 table 11-1 rc oscillator frequencies cext rext average fosc @ 5v,25 c 24pf 20k 2.02mhz 14.11% 33k 1.34mhz 11.50% 47k 0.952mhz 10.30% 100k 0.48mhz 9.07% 39pf 20k 1.536mhz 14.79% 33k 1.012mhz 11.67% 47k 0.72mhz 10.42% 100k 0.364mhz 9.75% 100pf 20k 0.78mhz 13.53% 33k 0.512mhz 10.35% 47k 0.364mhz 9.48% 100k 0.18mhz 7.34% typical rc o scillator 1.5 1.0 0.5 0 (mhz) f osc 2.5 3 4 5 6 v dd (v) frequency vs . v dd 2.5 2.0 3.5 4.5 5.5 ta=25 c r=20k r=33k r=47k r=100k typical rc oscillator 1.2 1.0 0.8 0 (m hz) f osc 2.5 3 4 5 6 v dd (v) frequency vs . v dd 1.6 1.4 3.5 4.5 5.5 r=20k r=47k r=100k 0.2 0.4 0.6 r=33k typical rc oscillator 0.6 0.5 0.4 0 (mhz) f osc 2.5 3 4 5 6 v dd (v) frequency vs . v dd 0.8 0.7 3.5 4.5 5.5 r=20k r=47k r=100k 0.1 0.2 0.3 r=33k typical r c o scillator 1.005 1.000 0.995 0.975 f osc 010305070 v dd (v) frequency vs . temperature 1.010 20 40 60 0.980 0.985 0.990 v dd =5v v dd =3v f osc (25 c) cext=24pf ta=25 c cext=39pf ta=25 c cext=100pf r=25k cext=24pf
gms81c1102 / gms81c1202 26 jan. 2002 ver 2.0 12. memory organization the gms81c1202 has separated address spaces for pro- gram memory and data memory. program memory can only be read, not written to. it can be up to 2k bytes of pro- gram memory. data memory can be read and written to up to 128 bytes including the stack area. 12.1 registers this device has six registers that are the program counter (pc), a accumulator (a), two index registers (x, y), the stack pointer (sp), and the program status word (psw). the program counter consists of 16-bit register. figure 12-1 configuration of registers ? accumulator the accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. the accumulator can be used as a 16-bit register with y register as shown below . figure 12-2 configuration of ya 16-bit register ? x, y registers in the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. these modes are ex- tremely effective for referencing subroutine tables and memory tables. the index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. ? stack pointer the stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. stack pointer iden- tifies the location in the stack to be accessed (save or re- store). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. the stack can be located at any position within 00 h to7f h of the internal data memory. the sp is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initial- ization routine. normally, the initial value of "7f h " is used . note: the stack pointer must be initialized by software be- cause its value is undefined after reset. example: to initialize the sp ldx #07fh txsp ; sp ? 7f h ? program counter the program counter is a 16-bit wide which consists of two 8-bit registers, pch and pcl. this counter indicates the address of the next instruction to be executed. in reset state, the program counter has reset routine address (pc h :0ff h , pc l :0fe h ). ? program status word the program status word (psw) contains several bits that reflect the current state of the cpu. the psw is described in figure 12-3. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. a accumulator x register y register stack pointer program counter program status word x y sp pcl pch psw two 8-bit registers can be used as a "ya" 16-bit register y a y a sp 0 stack address ( 000 h ~ 07f h ) 15 0 87 hardware fixed
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 27 [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithmetic operation and is also changed by the shift instruction or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. figure 12-3 psw (program status word) register [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all inter- rupts are disabled when cleared to "0". this flag immedi- ately becomes "0" when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector ad- dress. [overflow flag v] this flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. an overflow occurs when the result of an addition or subtraction ex- ceeds +127(7f h ) or -128(80 h ). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] this flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. when the bit in- struction is executed, bit 7 of memory is copied to this flag. n negative flag v - b h i z c msb lsb reset value : 00 h psw overflow flag brk flag carry flag receives zero flag interrupt enable flag carry out half carry flag receives carry out from bit 1 of addition operlands
gms81c1102 / gms81c1202 28 jan. 2002 ver 2.0 12.2 program memory a 16-bit program counter is capable of addressing up to 64k bytes, but this device has 2k bytes program memory space only the physically implemented. accessing a loca- tion above ffff h will cause a wrap-around to 0000 h . figure 12-4 shows a map of the upper part of the program memory. after reset, the cpu begins execution from reset vector which is stored in address fffe h , ffff h . as shown in figure 12-4, each area is assigned a fixed lo- cation in program memory. program memory area con- tains the user program, page call (pcall) area contains subroutine program, to reduce program byte length be- cause of using by 2 bytes pcall instead of 3 bytes call instruction. if it is frequently called, more useful to save program byte length. figure 12-4 program memory map the device configuration area can be programmed or left unprogrammed to select device configuration such as rc oscillation option. this area is not accessible during nor- mal execution but is readable and writable during program / verify. more detail informations are explained in device configu- ration area section. table call (tcall) causes the cpu to jump to each tcall address, where it commences execution of the service routine. the table call service locations are spaced at 2-byte interval : ffc0 h for tcall15, ffc2 h for tcall14, etc. the interrupt causes the cpu to jump to specific location, where it commences execution of the service routine. the external interrupt 0, for example, is assigned to location fffa h . the interrupt service locations are spaced at 2- byte interval : fff8 h for external interrupt 1, fffa h for external interrupt 0, etc. as for the area from ff00 h to ffff h , if any area of them is not going to be used, its service location is available as general purpose program memory. page call (pcall) area contains subroutine program to program memory pcall area tcall area interrupt vector area f800 h feff h ff00 h ffbf h ffc0 h ffdf h ffe0 h ffff h device not used 0f50 h 0f50 h 0ff0 h 0ff0 h id config configuration area 0f60 h id 0f70 h id 0f80 h id 0f90 h id 0fa0 h id 0fb0 h id 0fc0 h id 0fd0 h id 0fe0 h id address tcall name ffc0h ffc2h ffc4h ffc6h ffc8h ffcah ffcch ffceh ffd0h ffd2h ffd4h ffd6h ffd8h ffdah ffdch ffdeh tcall15 tcall14 tcall13 tcall12 tcall11 tcall10 tcall9 tcall8 tcall7 tcall6 tcall5 tcall4 tcall3 tcall2 tcall1 tcall0 / brk 1 1. the brk software interrupt is using same address with tcall0. table 12-1 tcall vectors address vector name ffe0h ffe2h ffe4h ffe6h ffe8h ffeah ffech ffeeh fff0h fff2h fff4h fff6h fff8h fffah fffch fffeh not used not used not used basic interval timer watchdog timer a/d converter not used not used not used not used timer / counter 1 timer / counter 0 external interrupt 1 external interrupt 0 not used reset table 12-2 interrupt vectors
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 29 reduce program byte length by using 2 bytes pcall in- stead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. the table call service area spaces 2-byte for every tcall: 0ffc0 h for tcall15, 0ffc2 h for tcall14, etc., as shown in figure 12-5 . example: usage of tcall figure 12-5 pcall and tcall memory area lda #5 tcall 0fh ; 1byte instruction :; instead of 3 bytes :; normal call ; ;table call routine ; func_a: lda lrg0 ret ; func_b: lda lrg1 ret ; ;table call add. area ; org 0ffc0h ; tcall address area dw func_a dw func_b 1 2 0ffc0 h c1 address program memory c2 c3 c4 c5 c6 c7 c8 0ff00 h address pcall area memory 0ffff h pcall area (256 bytes) * means that the brk software interrupt is using same address with tcall0. note: tcall 15 tcall 14 tcall 13 tcall 12 tcall 11 tcall 10 tcall 9 tcall 8 tcall 7 tcall 6 tcall 5 tcall 4 tcall 3 tcall 2 tcall 1 tcall 0 / brk * c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df
gms81c1102 / gms81c1202 30 jan. 2002 ver 2.0 pcall ? ? ? ? rel 4f35 pcall 35h tcall ? ? ? ? n 4a tcall 4 example: the usage software example of vector address and the initialize part. 4f ~ ~ ~ ~ next 35 0ff35h 0ff00h 0ffffh 11111111 11010110 01001010 pc: f h f h d h 6 h 4a ~ ~ ~ ~ 25 0ffd6h 0ff00h 0ffffh f1 next 0ffd7h ? 0f125h reverse org 0ffe0h dw not_used ; (0ffeo) dw not_used ; (0ffe2) dw not_used ; (0ffe4) dw bit_int ; (0ffe6) basic interval timer dw wdt_int ; (0ffe8) watchdog timer dw ad_int ; (0ffea) a/d dw not_used ; (0ffec) dw not_used ; (0ffee) dw not_used ; (0fff0) dw not_used ; (0fff2) dw tmr1_int ; (0fff4) timer-1 dw tmr0_int ; (0fff6) timer-0 dw int1 ; (0fff8) int.1 dw int0 ; (0fffa) int.0 dw not_used ; (0fffc) dw reset ; (0fffe) reset org 0f800h ;******************************************** ; main program * ;******************************************** ; reset: di ;disable all interrupts ldx #0 ram_clr: lda #0 ;ram clear(!0000h->!007fh) sta {x}+ cmpx #080h bne ram_clr ; ldx #07fh ;stack pointer initialize txsp ; call initial ; ; ldm ra, #0 ;normal port a ldm raio,#1000_0010b ;normal port direction ldm rb, #0 ;normal port b ldm rbio,#1000_0010b ;normal port direction : : ldm pfdr,#0 ;enable power fail detector :
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 31 12.3 data memory figure 12-6 shows the internal data memory space avail- able. data memory is divided into two groups, a user ram(including stack) and control registers. figure 12-6 data memory map internal data memory addresses are always one byte wide, which implies an address space of 128 bytes including the stack area. the stack pointer should be initialized within 00 h to 7f h by software because its value is undefined after reset. the stack area is defined at the data memory area, so the stack should not be overlapped by manipulating ram da- ta. for example, we assumed the stack pointer is 6f. if this address is accessed by program, the stack value is changed. so the malfunction is occurred. the control registers are used by cpu and peripheral func- tions for controlling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters, i/o ports. the control registers are in address c0 h to ff h . note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. more detail informations of each register are explained in each peripheral sections. note: write only registers can not be accessed by bit ma- nipulation instruction. do not use read-modify-write instruction. use byte manipulation instruction. example; to write at ckctlr ldm ckctlr,#09h ;divide ratio ? 16 table 12-3 reset value of control registers note: several names are given at same address. refer to below table. table 12-4 various register name in same adress data memory control registers 00 h 7f h c0 h ff h (including stack) address symbol r/w reset value c0h c1h c2h c3h c4h c5h cah cbh cch d0h d1h d1h d1h d2h d3h d3h d4h d4h d4h d5h deh e2h e3h e4h e5h e6h eah ebh ech ech edh efh ra raio rb rbio rc rcio rafunc rbfunc pupsel tm0 t0 tdr0 cdr0 tm1 tdr1 t1ppr t1 cdr1 t1pdr pwmhr bur ienh ienl irqh irql ieds adcm adcr bitr ckctlr wdtr pfdr r/w w r/w w r/w w w w w r/w r w r r/w w w r r r/w w w r/w r/w r/w r/w r/w r/w r r w r/w r/w undefined 0000_0000 undefined ---0_0000 undefined ----_--00 0000_0000 ---0_0000 ----_--00 --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 0000_---- 000-_---- 0000_---- 000-_---- ----_0000 --00_0001 undefined 0000_0000 -001_0111 0111_1111 ----_-100 addr. when read when write timer mode capture mode pwm mode timer mode pwm mode d1h t0 cdr0 - tdr0 - d3h - tdr1 t1ppr d4h t1 cdr1 t1pdr - t1pdr ech bitr ckctlr
gms81c1102 / gms81c1202 32 jan. 2002 ver 2.0 stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents of the pro- gram counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack location number for the next save.
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 33 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c0h ra ra port data register c1h raio ra port direction register c2h rb rb port data register c3h rbio rb port direction register c4h rc rc port data register c5h rcio rc port direction register cah rafunc ansel7 ansel6 ansel5 ansel4 ansel3 ansel2 ansel1 ansel0 cbh rbfunc - - - pwmo int1i int0i buzo avrefs cch pupsel - - - - - - pupsel1 pupsel0 d0h tm0 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st d1h t0/tdr0/ cdr0 timer0 register / timer data register 0 / capture data register 0 d2h tm1 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st d3h tdr1/ t1ppr timer data register 1/ pwm period register 1 d4h t1/cdr1/ t1pdr timer1 register / capture data register 1 / pwm duty register 1 d5h pwmhr pwm high register deh bur buck1 buck0 bur5 bur4 bur3 bur2 bur1 bur0 e2hienh int0eint1et0et1e---- e3hienl adewdtebite----- e4hirqhint0ifint1ift0ift1if---- e5hirql adifwdtifbitif----- e6hieds ----ied1hied1lied0hied0l eah adcm - - aden ads2 ads1 ads0 adst adsf ebh adcr adc result data register ech bitr 1 basic interval timer data register ech ckctlr note1 - wakeup rcwdt wdton btcl bts2 bts1 bts0 edh wdtr wdtcl 7-bit watchdog counter register efh pfdr 2 -----pfdispfdmpfds table 12-5 control registers of gms81c1202 these registers of shaded area can not be accessed by bit manipulation instruction as set1, clr1 , so should be accessed by register operation instruction as ldm dp,#imm . 1. the register bitr and ckctlr are located at same address. address ech is read as bitr, written to ckctlr. 2. the register pfdr only be implemented on devices, not on in-circuit emulator.
gms81c1102 / gms81c1202 34 jan. 2002 ver 2.0 12.4 addressing mode the gms87c1201 and gms81c1202 use six addressing modes. ? register addressing ? immediate addressing ? direct page addressing ? absolute addressing ? indexed addressing ? register-indirect addressing below example is shown for gms81c1202. (1) register addressing register addressing accesses the a, x, y, c and psw. (2) immediate addressing ? ? ? ? #imm in this mode, second byte (operand) is accessed as a data immediately. example: 0435 adc #35h e45535 ldm 35h,#55h (3) direct page addressing ? ? ? ? dp in this mode, a address is specified within direct page. example; c535 lda 35h ;a ? ram[35h] (4) absolute addressing ? ? ? ? !abs absolute addressing sets corresponding memory data to data , i.e. second byte(operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx, ldy, or, sbc, sta, stx, sty example; 0735f0 adc !0f035h ;a ? rom[0f035h] 35 a+35h+c ? a 04 memory e4 0f900 h data ? 55h ~ ~ ~ ~ data 0035 h 35 0f902 h 55 0f901 h ? data 35 0035 h 0f851 h data ? a ? ~ ~ ~ ~ c5 0f850 h 07 0f900 h ~ ~ ~ ~ data 0f035 h f0 0f902 h 35 0f901 h ? a+data+c ? a address: 0f035
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 35 the operation within data memory (ram) asl, bit, dec, inc, lsr, rol, ror example; addressing accesses the address 0035 h . 983500 inc !0035h ;a ? ram[035h] (5) indexed addressing x indexed direct page (no offset) ? ? ? ? {x} in this mode, a address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example; x=15 h d4 lda {x} ;acc ? ram[x]. x indexed direct page, auto increment ? ? ? ? {x}+ in this mode, a address is specified within direct page by the x register and the content of x is increased by 1. lda, sta example; x=35 h db lda {x}+ x indexed direct page (8 bit offset) ? ? ? ? dp+x this address value is the second byte (operand) of com- mand plus the data of -register. and it assigns the mem- ory in direct page. adc, and, cmp, eor, lda, ldy, or, sbc, sta sty, xma, asl, dec, inc, lsr, rol, ror example; x=015 h c645 lda 45h+x 98 0fa00 h ~ ~ ~ ~ data 0035 h 00 0fa02 h 35 0fa01 h ? data+1 ? data address: 0035 data d4 15 h 0fa50 h data ? a ? ~ ~ ~ ~ data db 35 h data ? a ? ~ ~ ~ ~ 36h ? x data 45 5a h 0fb51 h data ? a ? ~ ~ ~ ~ c6 0fb50 h 45h+15h=5ah
gms81c1102 / gms81c1202 36 jan. 2002 ver 2.0 y indexed direct page (8 bit offset) ? ? ? ? dp+y this address value is the second byte (operand) of com- mand plus the data of y-register, which assigns memory in direct page. this is same with above (2). use y register instead of x. y indexed absolute ? ? ? ? !abs+y sets the value of 16-bit absolute address plus y-register data as memory. this addressing mode can specify mem- ory in whole area. example; y=55 h d500fa lda !0fa00h+y (6) indirect addressing direct page indirect ? ? ? ? [dp] assigns data address to use for accomplishing command which sets memory data(or pair memory) by operand. also index can be used with index register x,y. jmp, call example; 3f35 jmp [35h] x indexed indirect ? ? ? ? [dp+x] processes memory data as data, assigned by 16-bit pair memory which is determined by pair data [dp+x+1][dp+x] operand plus x-register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example; x=10 h 1625 adc [25h+x] d5 0f900 h data ? a ~ ~ ~ ~ data 0fa55 h 0fa00h+55h=0fa55h fa 0f902 h 00 0f901 h ? 0a 35 h jump to address 0fc0a h ~ ~ ~ ~ 35 0fd00 h fc 36 h ? 3f 0fc0a h next ~ ~ ~ ~ 05 35 h 0f905 h ~ ~ ~ ~ 25 0fa00 h f9 36 h 16 0f905 h data ~ ~ ~ ~ a + data + c ? a 25 + x(10) = 35 h ?
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 37 y indexed indirect ? ? ? ? [dp]+y processes momory data as data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by operand in di- rect page plus y-register data. adc, and, cmp, eor, lda, or, sbc, sta example; y=10 h 1725 adc [25h]+y absolute indirect ? ? ? ? [!abs] the program jumps to address specified by 16-bit absolute address. jmp example; 1f25f9 jmp [!0f925h] 05 25 h 0f805 h + y(10) = 0f815 h ~ ~ ~ ~ 25 0fa00 h f8 26 h ? 17 0f815 h data ~ ~ ~ ~ a + data + c ? a e1 0f925 h jump to ~ ~ ~ ~ f9 0fa00 h f9 0f926 h ? 25 0f9e1 h next ~ ~ ~ ~ 1f program memory address 0f9e1 h
gms81c1102 / gms81c1202 38 jan. 2002 ver 2.0 13. i/o ports the gms81c1202 has three ports, ra, rb and rc. these ports pins may be multiplexed with an alternate function for the peripheral features on the device. in general, when a initial reset state, all ports are used as a general purpose input port. all pins have data direction registers which can set these ports as output or input. a 1 in the port direction register defines the corresponding port pin as output. conversely, write 0 to the corresponding bit to specify as an input pin. for example, to use the even numbered bit of ra as output ports and the odd numbered bits as input ports, write 55 h to address c1 h (ra direction register) during initial setting as shown in figure 13-1. reading data register reads the status of the pins whereas writing to it will write to the port latch. figure 13-1 example of port i/o assignment 13.1 ra and raio registers ra is an 8-bit bidirectional i/o port (address c0 h ). each port can be set individually as input and output through the raio register (address c1 h ). ra7~ra1 ports are multiplexed with analog input port ( an7~an1 ) and ra0 port is multiplexed with event counter input port ( ec0 ) . figure 13-2 registers of port ra the control register rafunc (address ca h ) controls to select alternate function. after reset, this value is "0", port may be used as general i/o ports. to select alternate func- tion such as analog input or external event counter input, write "1" to the corresponding bit of rafunc.regardless of the direction register raio, rafunc is selected to use as alternate functions, port pin can be used as a correspond- ing alternate features ( ra0/ec0 is controlled by rb- func ) i : input port write "55h" to port ra direction register 0 1 0 1 0 1 0 1 i o i o i o i o ra data rb data ra direction rb direction c0h c1h c2h c3h 76543210 bit 76543210port o : output port ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 input / output data ra data register ra address : c0h reset value : undefined ansel0 ra function selection register rafunc address : cah reset value : 00000000 ansel7 ansel1 ansel2 ansel3 ansel4 ansel5 ansel6 0 : rb0 1 : an0 0 : ra1 1 : an1 0 : ra2 1 : an2 0 : ra3 1 : an3 0 : ra4 1 : an4 0 : ra5 1 : an5 0 : ra6 1 : an6 0 : ra7 1 : an7 0 : input port 1 : output port direction select ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 ra direction register raio address : c1h reset value : 00000000 port rafunc.7~0 description ra7/an7 0 ra7 ( normal i/o port ) 1 an7 ( ads2~0=111 ) ra6/an6 0 ra6 ( normal i/o port ) 1 an6 ( ads2~0=110 ) ra5/an5 0 ra5 ( normal i/o port ) 1 an5 ( ads2~0=101 ) ra4/an4 0 ra4 ( normal i/o port ) 1 an4 ( ads2~0=100 ) ra3/an3 0 ra3 ( normal i/o port ) 1 an3 ( ads2~0=011 ) ra2/an2 0 ra2 ( normal i/o port ) 1 an2 ( ads2~0=010 ) ra1/an1 0 ra1 ( normal i/o port ) 1 an1 ( ads2~0=001 ) ra0/ec0 1 1. this port is not an analog input port , but event counter clock source input port. eco is controlled by setting tock2~0 = 111. the bit rafunc.0 (ansel0) controls the rb0/an0/avref port ( refer to port rb) . ra0 ( normal i/o port ) ec0 ( t0ck2~0=111 )
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 39 13.2 rb and rbio registers rb is a 5-bit bidirectional i/o port (address c2 h ). each pin can be set individually as input and output through the rbio register (address c3 h ). figure 13-3 registers of port rb in addition, port rb is multiplexed with various special features. the control register rbfunc (address cb h ) controls to select alternate function. after reset, this value is "0", port may be used as general i/o ports. to select al- ternate function such as external interrupt or timer com- pare output, write "1" to the corresponding bit of rbfunc. regardless of the direction register rbio, rbfunc is se- lected to use as alternate functions, port pin can be used as a corresponding alternate features. rb4 rb3 rb2 rb1 rb0 input / output data rb data register rb address : c2h reset value : undefined avrefs rb function selection register rbfunc address : cbh reset value : ---00000 buzo int0i int1i pwmo 0 : rb0 when ansel0 = 0, an0 when ansel0 = 1 0 : rb1 1 : buz output 0 : rb4 1 : pwm0 output or 0 : rb2 1 : int0 0 : rb3 1 : int1 pup0 pull-up selection register pupsel address : cch reset value : ------00 - pup1 - - - 0 : no pull-up 1 : with pull-up 0 : no pull-up 1 : with pull-up ied0l interrupt edge selection register ieds address : e6h reset value : ----0000 ied0h ied1l ied1h external interrupt edge select int0 int1 00 : normal i/o port 01 : falling ( 1-to-0 transition ) 10 : rising ( 0-to-1 transition ) 11 : both ( rising & falling ) compare output rb2 / int0 pull-up rb3 / int1 pull-up 1 : avref 0 : input port 1 : output port direction select - - - rb4 rb3 rb2 rb1 rb0 rb direction register rbio address : c3h reset value : ---00000 the shaded areas are only related with in gms81c1202. so in gms81c1102, this area must be written to 0. port rbfunc.4~0 description rb4/ pwm0/ comp0 0 rb4 ( normal i/o port ) 1 pwm0 output / timer1 compare output rb3/int1 0 rb3 ( normal i/o port ) 1 external interrupt input 1 rb2/int0 0 rb2 ( normal i/o port ) 1 external interrupt input 0 rb1/buz 0 rb1 ( normal i/o port ) 1 buzzer output rb0/an0/ avref 0 1 rb0 ( normal i/o port ) / an0 (ansel0=1) 1 2 external analog reference voltage 1. when ansel0 = "0", this port is defined for normal i/o port ( rb0 ). when ansel0 = "1" and ads2~0 = " 000", this port can be used analog input port ( an0 ). 2. when this bit set to "1", this port defined for avref , so it can not be used analog input port an0 and normal i/o port rb0.
gms81c1102 / gms81c1202 40 jan. 2002 ver 2.0 13.3 rc and rcio registers rc is an 4-bit bidirectional i/o port (address c4 h ). each pin can be set individually as input and output through the rcio register (address c5 h ). figure 13-4 registers of port rc - rc1 rc0 input / output data 0 : input port 1 : output port direction select rc data register rc address : c4h reset value : undefined rc1 rc0 rc direction register rcio address : c5h reset value : ------00 - ---- -- ----
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 41 14. clock generator the clock generator produces the basic clock pulses which provide the system clock to be supplied to the cpu and pe- ripheral hardware. the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator connected to the xin and xout pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the xin pin and open the xout pin figure 14-1 block diagram of clock pulse generator 14.1 oscillation circuit x in and x out are the input and output, respectively, a in- verting amplifier which can be set for use as an on-chip os- cillator, as shown in figure 14-2 . figure 14-2 oscillator connections to drive the device from an external clock source, xout should be left unconnected while xin is driven as shown in figure 14-3. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. oscillation circuit is designed to be used either with a ce- ramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components in addition, the gms81c1202 has an ability for the exter- nal rc oscillated operation. it offers additional cost sav- ings for timing insensitive applications . the rc oscillator frequency is a function of the supply voltage, the external resistor (rext) and capacitor (cext) values, and the operating temperature. the user needs to take into account variation due to toler- ance of external r and c components used. figure 14-4 shows how the rc combination is connected to the gms81c1202. figure 14-3 external clock connections note: when using a system clock oscillator, carry out wir- ing in the broken line area in figure 14-2 to prevent any effects from wiring capacities. - minimize the wiring length. - do not allow wiring to intersect with other signal conductors. - do not allow wiring to come near changing high current. - set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground to any ground pattern where high current is present. - do not fetch signals from the oscillator. internal system clock prescaler clock pulse ? 1 peripheral clock ? 2 ? 4 ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 generator ? 2048 stop wakeup fxin oscillation circuit xout xin vss c1 c2 recommended: c1, c2 = 30pf 10pf for crystals r1 r1 = 1m w xout xin vss open external clock source
gms81c1102 / gms81c1202 42 jan. 2002 ver 2.0 figure 14-4 rc oscillator connections the oscillator frequency, divided by 4, is output from the xout pin, and can be used for test purpose or to synchroze other logic. to set the rc oscillation, it should be programmed rcopt bit to "1" to config (0ff0 h ). ( refer to de- vice configuration area ) note: when using a system clock oscillator, carry out wir- ing in the broken line area in figure 14-2 to prevent any effects from wiring capacities. - minimize the wiring length. - do not allow wiring to intersect with other signal conductors. - do not allow wiring to come near changing high current. - set the potential of the grounding position of the os- cillator capacitor to that of v ss . do not ground to any ground pattern where high current is present. - do not fetch signals from the oscillator . xout xin vdd cext fxin ? 4 rext
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 43 15. basic interval timer the gms81c1202 has one 8-bit basic interval timer that is free-run, can not stop. block diagram is shown in figure 15-1 .the 8-bit basic interval timer register (bitr) is in- creased every internal count pulse which is divided by prescaler. since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. as the count overflows from ff h to 00 h , this overflow causes to generate the basic interval timer interrupt. the bitf is interrupt request flag of basic interval timer. when write "1" to bit btcl of ckctlr, bitr register is cleared to "0" and restart to count-up. the bit btcl be- comes "0" after one machine cycle by hardware. if the stop instruction executed after writing "1" to bit wakeup of ckctlr, it goes into the wake-up timer mode. in this mode, all of the block is halted except the os- cillator, prescaler ( only fxin ? 2048 ) and timer0. if the stop instruction executed after writing "1" to bit rcwdt of ckctlr, it goes into the internal rc oscillat- ed watchdog timer mode. in this mode, all of the block is halted except the internal rc oscillator, basic interval timer and watchdog timer. more detail informations are explained in power saving function. the bit wdton de- cides watchdog timer or the normal 7-bit timer note: all control bits of basic interval timer are in ckctlr register which is located at same address of bitr (address ec h ). address ec h is read as bitr, writ- ten to ckctlr. therefore, the ckctlr can not be accessed by bit manipulation instruction. . figure 15-1 block diagram of basic interval timer figure 15-2 ckctlr : clock control register ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 stop wakeup 0 1 mux 8 3 fxin bitr (8bit) bitif bts[2:0] rcwdt internal rc osc basic interval timer interrupt btcl clear to watchdog timer clock control register ckctlr address : ech reset value : -0010111 - wakeup rcwdt wdton btcl bts2 bts1 bts0 basic interval timer clock selection 000 : fxin ? 8 001 : fxin ? 16 100 : fxin ? 128 101 : fxin ? 256 110 : fxin ? 512 111 : fxin ? 1024 010 : fxin ? 32 011 : fxin ? 64 symbol function description wakeup 1: enables wake-up timer 0: disables wake-up timer rcwdt 1: enables internal rc watchdog timer 0: disables internal rc watchdog time wdton 1: enables watchdog timer 0: operates as a 7-bit timer btcl 1: bitr is cleared and btcl becomes "0" automatically after one machine cycle, and bitr continue to count-up bit manipulation not available
gms81c1102 / gms81c1202 44 jan. 2002 ver 2.0 16. timer / counter the gms81c1202 has two timer/counter registers. each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). timer 0 and timer 1 can be used either the two 8-bit tim- er/counter or one 16-bit timer/counter by combining them. in the "timer" function, the register is increased every in- ternal clock input. thus, one can think of it as counting in- ternal clock input. since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in timer0. and timer1 can use the same clock source too. in addition, timer1 has more fast clock source ( 1/1 to 1/8 ). in the "counter" function, the register is increased in re- sponse to a 0-to-1 (rising edge) transition at its correspond- ing external input pin, ec0. and in the "capture" function, the register is increased in response external interrupt same with timer function. when external interrupt edge input, the count register is captured into capture data register cdrx. timer1 is shared with "pwm" function and "compare out- put" function it has seven operating modes: "8-bit timer/counter", "16- bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", "16-bit compare output" and "10-bit pwm" which are selected by bit in timer mode register tm0 and tm1 as shown in figure 16-1 and table 16-1. figure 16-1 timer 0 and timer 1 mode register timer 0 mode register tm0 address : d0h reset value : --000000 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st timer 1 mode register tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st cap0 capture mode selection bit . 0 : disables capture 1 : enables capture t0cn continue control bit 0 : stop counting 1 : start counting continuously t0ck[2:0] input clock selection 000 : fxin ? 2 100 : fxin ? 128 001 : fxin ? 4 101 : fxin ? 512 010 : fxin ? 8 110 : fxin ? 2048 011 : fxin ? 32 111 : external event ( ec0 ) t0st start control bit 0 : stop counting 1 : start countingn pol pwm output polarity 0 : duty active low 1 : duty active high t1ck[2:0] input clock selection 00 : fxin 10 : fxin ? 8 01 : fxin ? 2 11 : using the timer 0 clock 16bit 16-bit mode selection 0 : 8-bit mode 1 : 16-bit mode t1cn continue control bit 0 : stop counting 1 : start counting continuously pwme pwm enable bit 0 : disables pwm 1 : enables pwm t1st start control bit 0 : stop counting 1 : start countingn cap1 capture mode selection bit . 0 : disables capture 1 : enables capture
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 45 16.1 8-bit timer/counter mode the gms81c1202 has two 8-bit timer/counters, timer 0 and timer 1, as shown in figure 16-2 . the "timer" or "counter" function is selected by mode reg- isters tm0, tm1 as shown in figure 16-1 and table 16-1 . to use as an 8-bit timer/counter mode, bit cap0 of tm0 is cleared to "0" and bits 16bit of tm1 should be cleared to 0(table 16-1). figure 16-2 8-bit timer / counter mode 16bit cap0 cap1 pwme t0ck[2:0] t1ck[1:0] pwmo 1 timer 0 timer1 0000xxx xx 08-bit timer 8-bit timer 0010 111 xx 08-bit event counter8-bit capture 0100xxx xx 18-bit capture 8-bit compare output 0001xxx xx 18-bit timer/counter10-bit pwm 1000xxx 11 0 16-bit timer 1000 111 11 0 16-bit event counter 11 x 2 0 xxx 11 0 16-bit capture 1000xxx 11 1 16-bit compare output table 16-1 operating modes of timer 0 and timer 1 1. this bit is the bit4 of rb function register(rbfunc). 2. x : the value is 0 or 1 corresponding your operation. ? 1 ? 2 ? 8 tm0 address : d0h reset value : --000000 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st -- 0 xxxxx x 000 xxxx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 fxin ec0 edge detector mux mux 1 1 t0 ( 8-bit ) tdr0 ( 8-bit ) t0if clear comparator timer 0 interrupt t1 ( 8-bit ) tdr1 ( 8-bit ) t1if clear comparator timer 1 interrupt t0st 0 : stop 1 : start t1st 0 : stop 1 : start t0cn t1cn t0ck[2:0] t1ck[1:0] f/f comp0 pin ? 2048 x : the value "0" or "1" corresponding your operation.
gms81c1102 / gms81c1202 46 jan. 2002 ver 2.0 these timers have each 8-bit count register and data regis- ter. the count register is increased by every internal or ex- ternal clock input. the internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by con- trol bits t0ck2, t0ck1 and t0ck0 of register tm0) and 1, 2, 8 (selected by control bits t1ck1 and t1ck0 of reg- ister tm1). in the timer 0, timer register t0 increases from 00 h until it matches tdr0 and then reset to 00 h . the match output of timer 0 generates timer 0 interrupt (latched in t0f bit). as tdrx and tx register are in same address, when reading it as a tx, written to tdrx. in counter function, the counter is increased every 0-to 1 (rising edge) transition of ec0 pin. in order to use counter function, the bit ra0 of the ra direction register raio is set to "0". the timer 0 can be used as a counter by pin ec0 input, but timer 1 can not. figure 16-3 counting example of timer data registers figure 16-4 timer count operation ~ ~ timer 1 (t1if) interrupt tdr1 time interrupt occurs interrupt period up- c ount ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 9 n n-1 p cp = p cp x (n+1) interrupt occurs interrupt occurs timer 1 (t1if) interrupt tdr1 time stop clear & start disable enable start & stop t1st t1cn control count up-c o unt ~ ~ ~ ~ t1st = 0 t1st = 1 t1cn = 0 t1cn = 1 interrupt occurs interrupt occurs
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 47 16.2 16-bit timer/counter mode the timer register is being run with 16 bits. a 16-bit timer/ counter register t0, t1 are increased from 0000 h until it matches tdr0, tdr1 and then resets to 0000 h . the match output generates timer 0 interrupt not timer 1 in- terrupt. the clock source of the timer 0 is selected either internal or external clock by bit t0ck2, t0ck1 and t0sl0. in 16-bit mode, the bits t1ck1,t1ck0 and 16bit of tm1 should be set to "1" respectively. figure 16-5 16-bit timer / counter mode 16.3 8-bit compare output ( 16-bit ) the gms87c1201 and gms81c1202 has a function of timer compare output. to pulse out, the timer match can goes to port pin( comp0 ) as shown in figure 16-2 and figure 16-5 . thus, pulse out is generated by the timer match. these operation is implemented to pin, rb4/ comp0/pwm. this pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation. in this mode, the bit pwmo of rb function register (rb- func) should be set to "1", and the bit pwme of timer1 mode register ( tm1 ) should be set to "0". in addition, 16-bit compare output mode is also available. 16.4 8-bit capture mode the timer 0 capture mode is set by bit cap0 of timer mode register tm0 (bit cap1 of timer mode register tm1 for timer 1) as shown in figure 16-6. as mentioned above, not only timer 0 but timer 1 can also be used as a capture mode. the timer/counter register is increased in response inter- nal or external input. this counting function is same with normal timer mode, and timer interrupt is generated when timer register t0 (t1) increases and matches tdr0 (tdr1). tm0 address : d0h reset value : --000000 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st -- 0 xxxxx x 10011 xx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 fxin ec0 edge detector mux 1 t1 ( 8-bit ) tdr1 ( 8-bit ) t0if clear comparator timer 0 interrupt t0 ( 8-bit ) tdr0 ( 8-bit ) t0st 0 : stop 1 : start t0cn t0ck[2:0] f/f comp0 pin ? 2048 x : the value "0" or "1" corresponding your operation. oscillation frequency 2 prescaler value tdr 1 ) + ( -------------------------------------------------------------------------------- =
gms81c1102 / gms81c1202 48 jan. 2002 ver 2.0 this timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of timer. for example, in figure 16-8 , the pulse width of captured signal is wider than the timer data value (ff h ) over 2 times. when external interrupt is occured, the captured value (13 h ) is more little than wanted value. it can be ob- tained correct value by counting the number of timer over- flow occurence. timer/counter still does the above, but with the added fea- ture that a edge transition at external input intx pin causes the current value in the timer x register (t0,t1), to be cap- tured into registers cdrx (cdr0, cdr1), respectively. after captured, timer x register is cleared and restarts by hardware. it has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register ieds (refer to external interrupt section). in ad- dition, the transition at intx pin generate an interrupt. note: the cdrx, tdrx and tx are in same address. in the capture mode, reading operation is read the cdrx, not tx because path is opened to the cdrx, and tdrx is only for writing operation. figure 16-6 8-bit capture mode ? 1 ? 2 ? 8 tm0 address : d0h reset value : --000000 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st -- 1 xxxxx x 001 xxxx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 fxin ec0 edge detector mux mux 1 1 t0 ( 8-bit ) cdr0 ( 8-bit ) t0if clear comparator timer 0 interrupt t0st 0 : stop 1 : start t0cn t1cn t0ck[2:0] t1ck[1:0] tdr0 ( 8-bit ) int0if int 0 interrupt int0 t1 ( 8-bit ) cdr1 ( 8-bit ) t1if clear comparator timer 1 interrupt tdr1 ( 8-bit ) int1if int 1 interrupt int1 t0st 0 : stop 1 : start ieds[1:0] ieds[3:2] capture capture ? 2048
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 49 figure 16-7 input capture operation figure 16-8 excess timer overflow in capture mode ~ ~ ext. int0 pin interrupt request t0 time up - coun t ~ ~ ~ ~ 0 1 2 3 4 5 6 7 8 9 n n-1 capture ( timer stop ) clear & start interrupt interval period delay ( int0f ) ext. int0 pin interrupt request ( int0f ) this value is loaded to cdr0 interrupt interval period = ff h + 01 h + ff h +01 h + 13 h = 213 h ff h ff h ext. int0 pin interrupt request ( int0f ) 00 h 00 h interrupt request ( t0f ) t0 13 h
gms81c1102 / gms81c1202 50 jan. 2002 ver 2.0 16.5 16-bit capture mode 16-bit capture mode is the same as 8-bit capture, except that the timer register is being run will 16 bits. the clock source of the timer 0 is selected either internal or external clock by bit t0ck2, t0ck1 and t0ck0. in 16-bit mode, the bits t1ck1,t1ck0 and 16bit of tm1 should be set to "1" respectively. figure 16-9 16-bit capture mode 16.6 pwm mode the gms81c1202 has a two high speed pwm (pulse width modulation) functions which shared with timer1. in pwm mode, pin rb4/comp0/pwm0 outputs up to a 10-bit resolution pwm output. this pin should be defined as a pwm output by setting "1" bit pwmo in rbfunc register. the period of the pwm output is determined by the t1ppr (pwm0 period register) and pwm0hr[3:2] (bit3,2 of pwm0 high register) and the duty of the pwm output is determined by the t1pdr (pwm0 duty regis- ter) and pwm0hr[1:0] (bit1,0 of pwm0 high register). the user writes the lower 8-bit period value to the t1ppr and the higher 2-bit period value to the pwm0hr[3:2]. and writes duty value to the t1pdr and the pwm0hr[1:0] same way. the t1pdr is configured as a double buffering for glitch- less pwm output. in figure 16-10 , the duty data is trans- fered from the master to the slave when the period data matched to the counted value. ( i.e. at the beginning of next duty cycle ) pwm period = [ pwm0hr[3:2]t1ppr ] x source clock pwm duty = [ pwm0hr[1:0]t1pdr ] x source clock the relation of frequency and resolution is in inverse pro- portion. table 16-2 shows the relation of pwm frequency vs. resolution. tm0 address : d0h reset value : --000000 - - cap0 t0ck2 t0ck1 t0ck0 t0cn t0st tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st -- 1 xxxxx x 10 x 11 xx ? 2 ? 4 ? 128 ? 512 ? 8 ? 32 fxin ec0 edge detector mux 1 t0 + t1 ( 16-bit ) tdr1 t0if clear comparator timer 0 interrupt t0st 0 : stop 1 : start t0cn t0ck[2:0] tdr0 int0if int 0 interrupt int0 ieds[1:0] capture cdr1 cdr0 ( 8-bit ) ( 8-bit ) ( 8-bit ) ( 8-bit ) ? 2048 x : the value "0" or "1" corresponding your operation.
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 51 if it needed more higher frequency of pwm, it should be reduced resolution. the bit pol of tm1 decides the polarity of duty cycle. if the duty value is set same to the period value, the pwm output is determined by the bit pol ( 1: high, 0: low ). and if the duty value is set to "00 h ", the pwm output is determined by the bit pol ( 1: low, 0: high ). it can be changed duty value when the pwm output. how- erver the changed duty value is output after the current pe- riod is over. and it can be maintained the duty value at present output when changed only period value shown as figure 16-12 . as it were, the absolute duty time is not changed in varying frequency. but the changed period val- ue must greater than the duty value note: at pwm output start command, one first pulse would be output abnormally. because if user writes regis- ter values while timer is in operaiton, these register could be set with certain values at first. to prevent this operation, user must stop pwm timer clock and then set the duty and the period register values. . figure 16-10 pwm mode resolution frequency t1ck[1:0] = 00(125ns) t1ck[1:0] = 01(250ns) t1ck[1:0] = 10(1us) 10-bit 7.8khz 3.9khz 0.98khz 9-bit 15.6khz 7.8khz 1.95khz 8-bit 31.2khz 15.6khz 3.90khz 7-bit 62.5khz 31.2khz 7.81khz table 16-2 pwm frequency vs. resolution at 8mhz ? 1 ? 2 ? 8 pwm0hr address : d5h reset value : ----0000 - - - - pwm0hr3 pwm0hr2 pwm0hr1 pwm0hr0 ---- xxxx mux 1 t1cn t1ck[1:0] t1 ( 8-bit ) t1st 0 : stop 1 : start clear comparator comparator t1pdr(8-bit) pwm0hr[1:0] t1ppr(8-bit) pwm0hr[3:2] t1pdr(8-bit) sq r pol pwm0o rb4/ pwm0 t0 clock source fxin tm1 address : d2h reset value : 00000000 pol 16bit pwme cap1 t1ck1 t1ck0 t1cn t1st x010 xxxx [rbfunc.4] period high duty high slave master bit manipulation not available x : the value is "0" or "1" corresponding your operation.
gms81c1102 / gms81c1202 52 jan. 2002 ver 2.0 figure 16-11 example of pwm at 8mhz figure 16-12 example of changing the period in absolute duty cycle (@8mhz) fxin t1 pwm ~ ~ ~ ~ ~ ~ 01 02 03 04 05 7f 80 81 3ff 02 03 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ pol=1 pwm pol=0 duty cycle [ 80h x 125ns = 16us ] period cycle [ 3ffh x 125ns = 127.875us, 7.8khz ] pwm0hr = 0ch t1ppr = ffh t1pdr = 80h t1ck[1:0] = 00 ( fxin ) pwm0hr3 pwm0hr2 pwm0hr1 pwm0hr0 t1ppr (8-bit) t1pdr (8-bit) period duty 11 ffh 00 80h 00 01 00 source t1 pwm pol=1 duty cycle period cycle [ 0eh x 1us = 14us, 71khz ] pwmhr = 00h t1ppr = 0eh t1pdr = 05h t1ck[1:0] = 10 ( 1us ) 01 02 03 04 05 06 08 09 0b 0c 0d 0e 01 02 03 04 05 06 07 08 09 0a 01 02 03 04 07 0a 05 [ 05h x 1us = 5us ] duty cycle [ 05h x 1us = 5us ] period cycle [ 0ah x 1us = 10us, 100khz ] duty cycle [ 05h x 1us = 5us ] write t1ppr to 0ah period changed clock
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 53 17. buzzer output function the buzzer driver consists of 6-bit binary counter, the buzzer register bur and the clock selector. it generates square-wave which is very wide range frequency (480 hz~250 khz at fxin = 4 mhz) by user programmable counter. pin rb1 is assigned for output port of buzzer driver by set- ting the bit buzo of rbfunc to "1". the 6-bit buzzer counter is cleared and start the counting by writing signal to the register bur. it is increased from 00h until it matches 6-bit register bur. also, it is cleared by counter overflow and count up to out- put the square wave pulse of duty 50%. the bit 0 to 5 of bur determines output frequency for buzzer driving. frequency calculation is following as shown below. the bits buck1, buck0 of bur selects the source clock from prescaler output. figure 17-1 buzzer driver () oscillator frequency 2 prescaler ratio bur 1 + () ------------------------------------------------------------------------------ = bur address : deh reset value : 11111111 buck1 buck0 bur5 bur4 bur3 bur2 bur1 bur0 ? 64 ? 16 ? 32 fxin mux counter ( 6-bit ) bur ( 6-bit ) f/f comparator buck[1:0] rb1/buz pin ? 8 input clock selection 00 : fxin ? 8 01 : fxin ? 16 10 : fxin ? 32 11 : fxin ? 64 buzzer period data buzo [rbfunc.1] bit manipulation not available
gms81c1102 / gms81c1202 54 jan. 2002 ver 2.0 18. analog to digital converter the analog-to-digital converter (a/d) allows conversion of an analog input signal to a corresponding 8-bit digital value. the a/d module has eight analog inputs, which are multiplexed into one sample and hold. the output of the sample and hold is the input into the converter, which gen- erates the result via successive approximation. the analog reference voltage is selected to v dd or avref by setting of the bit avrefs in rbfunc register. if ex- ternal analog reference avref is selected, the bit ansel0 should not be set to "1", because this pin is used to an ana- log reference of a/d converter. the a/d module has two registers which are the control register adcm and a/d result register adcr. the adcm register, shown in figure 18-2 , controls the oper- ation of the a/d converter module. the port pins can be configured as analog inputs or digital i/o. to use analog inputs, each port is assigned analog input port by setting the bit ansel[7:0] in rafunc register. and selected the corresponding channel to be converted by setting ads[2:0]. the processing of conversion is start when the start bit adst is set to "1". after one cycle, it is cleared by hard- ware. the register adcr contains the results of the a/d conversion. when the conversion is completed, the result is loaded into the adcr, the a/d conversion status bit adsf is set to "1", and the a/d interrupt flag adif is set. the block diagram of the a/d module is shown in figure 18-1. the a/d status bit adsf is set automatically when a/d conversion is completed, cleared when a/d conver- sion is in process. the conversion time takes maximum 10 us (at fxin=8 mhz). figure 18-1 a/d converter block diagram rb0/an0/avref ansel0 ( rafunc.0 ) ra1/an1 ansel1 ra2/an2 ansel2 ra3/an3 ansel3 ra4/an4 ansel4 ra5/an5 ansel5 ra6/an6 ansel6 ra7/an7 ansel7 000 001 010 011 100 101 110 111 v dd pin 1 0 avrefs ( rbfunc.0 ) aden s/h successive approximation circuit adif resistor ladder circuit ads[2:0] adcr(8-bit) sample & hold a/d interrupt address : ebh reset value : undefined a/d result register
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 55 figure 18-2 a/d converter registers figure 18-3 a/d converter operation flow a/d converter cautions (1) input range of an0 to an7 the input voltages of an0 to an7 should be within the specification range. in particular, if a voltage above vdd (or avref) or below v ss is input (even if within the absolute max- imum rating range), the conversion value for that channel can not be indeterminate. the conversion values of the other channels may also be affected. (2) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on pins avref(or vdd)and an0 to an7. since the effect increases in proportion to the output impedance of the an- alog input source, it is recommended that a capacitor be con- nected externally as shown in figure 18-4 in order to reduce noise . figure 18-4 analog input pin connecting capacitor adcm address : eah reset value : --000001 - - aden ads2 ads1 ads0 adst adsf reserved analog channel select a/d status bit 0 : a/d conversion is in process 1 : a/d conversion is completed a/d start bit 1 : a/d conversion is started after 1 cycle, cleared to "0" 0 : bit force to zero 000 : channel 0 ( rb0/an0 ) 001 : channel 1 ( ra1/an1 ) 010 : channel 2 ( ra2/an2 ) 011 : channel 3 ( ra3/an3) 100 : channel 4 ( ra4/an4 ) 101 : channel 5 ( ra5/an5 ) 110 : channel 6 ( ra6/an6 ) 111 : channel 7 ( ra7/an7 ) a/d enable bit 1 : a/d conversion is enable 0 : a/d converter module shut off and consumes no operation current a/d control register adcr address : ebh reset value : undefined adcr7 adcr6 adcr5 adcr4 adcr3 adcr2 adcr1 adcr0 a/d result data register enable a/d converter a/d start ( adst = 1 ) nop adsf = 1 a/d input channel select analog reference select read adcr yes no an0~an7 100~1000pf analog input
gms81c1102 / gms81c1202 56 jan. 2002 ver 2.0 (3) pins an0/rb0 and an1/ra1 to an7/ra7 the analog input pins an0 to an7 also function as input/ output port (port ra and rb0) pins. when a/d conver- sion is performed with any of pins an0 to an7 selected, be sure not to execute a port input instruction while con- version is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. (4) av ref pin input impedance a series resistor string of approximately 10k w is connected be- tween the av ref pin and the v ss pin. therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the av ref pin and the v ss pin, and there will be a large reference voltage error.
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 57 19. interrupts the gms81c1202 interrupt circuits consist of interrupt enable register (ienh, ienl), interrupt request flags of irqh, irql, interrupt edge selection register (ieds), priority circuit and master enable flag("i" flag of psw). the configuration of interrupt circuit is shown in figure 19-1 and interrupt priority is shown in table 19-1 . the external interrupts int0 and int1 can each be transi- tion-activated (1-to-0, 0-to-1 and both transiton). the flags that actually generate these interrupts are bit int0ifand int1if in register irqh. when an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. the timer 0 and timer 1 interrupts are generated by t0if, t1if, which are set by a match in their respective timer/ counter register. the ad converter interrupt is generated by adif which is set by finishing the analog to digital con- version. the watch dog timer interrupt is generated by wdtif which set by a match in watch dog timer register ( when the bit wdton is set to "0"). the basic interval timer interrupt is generated by bitif which is set by a overflowing of the basic interval timer register(bitr). . figure 19-1 block diagram of interrupt function the interrupts are controlled by the interrupt master enable flag i-flag (bit 2 of psw), the interrupt enable register (ienh, ienl) and the interrupt request flags (in irqh, irql) except power-on reset and software brk interrupt. interrupt enable registers are shown in figure 19-2 . these registers are composed of interrupt enable flags of each in- terrupt source, these flags determines whether an interrupt will be accepted or not. when enable flag is "0", a corre- sponding interrupt source is prohibited. note that psw contains also a master enable bit, i-flag, which disables all interrupts at once. bit bitif wdtif wdt a/d converter timer 1 timer 0 external int. 1 external int. 0 ienh interrupt enable interrupt enable irqh irql interrupt vector address generator internal bus line register (lower byte) internal bus line register (higher byte) release stop to cpu interrupt master enable flag i flag ienl priority control i-flag is in psw, it is cleared by di, set by ei instruction.when it goes interrupt service, i-flag is cleared by hardware, thus any other interrupt are inhibited. when interrupt service is completed by reti instruction, i-flag is set to 1 by hardware. int0if int1if t0if t1if adif 7 6 5 4 7 6 5 ieds reset/interrupt symbol priority vector addr. hardware reset external interrupt 0 external interrupt 1 timer 0 timer 1 a/d converter watch dog timer basic interval timer reset int0 int1 timer 0 timer 1 a/d c wdt bit - 1 2 3 4 5 6 7 fffe h fffa h fff8 h fff6 h fff4 h ffea h ffe8 h ffe6 h table 19-1 interrupt priority
gms81c1102 / gms81c1202 58 jan. 2002 ver 2.0 figure 19-2 interrupt enable registers and interrupt request registers when an interrupt is occured, the i-flag is cleared and dis- able any further interrupt, the return address and psw are pushed into the stack and the pc is vectored to. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits. the interrupt request flag bit(s) must be cleared by soft- ware before re-enabling interrupts to avoid recursive inter- rupts. the interrupt request flags are able to be read and written. 19.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an in- struction. interrupt acceptance sequence requires 8 f osc (2 m s at f xin =4mhz) after the completion of the current in- struction execution. the interrupt service task is terminat- ed upon execution of an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. when a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to "0". 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at the entry address of the inter- rupt service program is executed. ienh address : e2h reset value : 0000---- int0e int1e t0e t1e - - - - interrupt enable register high ienl address : e3h reset value : 000----- ade wdte bite - - - - - interrupt enable register low irqh address : e4h reset value : 0000---- int0if int1if t0if t1if - - - - interrupt request register high irql address : e5h reset value : 000----- adif wdtif bitif - - - - - interrupt request register low 0 : disable 1 : enable enables or disables the interrupt individually if flag is cleared, the interrupt is disabled. 0 : not occurred 1 : interrupt request is occurred shows the interrupt occurrence
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 59 figure 19-3 timing chart of interrupt acceptance and interrupt return instruction a interrupt request is not accepted until the i-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, the i-flag should be set to "1" by ei instruction in the interrupt service program. in this case, acceptable interrupt sources are se- lectively enabled by the individual interrupt enable flags. saving/restoring general-purpose register during interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. these registers are saved by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. the following method is used to save/restore the general- purpose registers. example: register save using push and pop instructions general-purpose register save/restore using push and pop instructions; v.l. system clock address bus pc sp sp-1 sp-2 v.h. new pc v.l. data bus not used pch pcl psw adl op code adh instruction fetch internal read internal write interrupt processing step interrupt service task v.l. and v.h. are vector addresses. adl and adh are start addresses of interrupt service routine as vector contents. basic interval timer 012 h 0e3 h 0ffe6 h 0ffe7 h 0e h 2e h 0e312 h 0e313 h entry address correspondence between vector table address for bit interrupt and the entry address of the interrupt service program. vector table address intxx: push a push x push y ;save acc. ;save x reg. ;save y reg. interrupt processing pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return
gms81c1102 / gms81c1202 60 jan. 2002 ver 2.0 19.2 brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk interrupt is generated, b-flag of psw is set to distin- guish brk from tcall 0. each processing step is determined by b-flag as shown in figure 19-4. figure 19-4 execution of brk/tcall0 19.3 multi interrupt if two requests of different priority levels are received si- multaneously, the request of higher priority level is ser- viced. if requests of the interrupt are received at the same time simultaneously, an internal polling sequence deter- mines by hardware which request is serviced. however, multiple processing through software for special features is possible. generally when an interrupt is accept- ed, the i-flag is cleared to disable any further interrupt. but as user sets i-flag in interrupt routine, some further inter- rupt can be serviced even if certain interrupt is in progress. example: even though timer1 interrupt is in progress, int0 interrupt serviced without any suspend. timer1: push a push x push y ldm ienh,#80h ; enable int0 only ldm ienl,#0 ; disable other ei ; enable interrupt : : : : : : ldm ienh,#0ffh ; enable all interrupts ldm ienl,#0f0h pop y pop x pop a reti figure 19-5 execution of multi interrupt b-flag brk interrupt routine reti tcall0 routine ret brk or tcall0 =0 =1 enable int0 timer 1 service int0 service main program service occur timer1 interrupt occur int0 ei disable other enable int0 enable other in this example, the int0 interrupt can be serviced without any pending, even timer1 is in progress. because of re-setting the interrupt enable registers ienh,ienl and master enable "ei" in the timer1 routine.
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 61 19.4 external interrupt the external interrupt on int0 and int1 pins are edge triggered depending on the edge selection register ieds (address 0e6 h ) as shown in figure 19-6 . the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge . figure 19-6 external interrupt block diagram example: to use as an int0 and int1 : : ; **** set port as an input port rb2,rb3 ldm rbio,#1111_0011b ; ; ; **** set port as an interrupt port ldm rbfunc,#0c0h ; ; ; **** set falling-edge detection ldm ieds,#0000_0101b : : response time the int0 and int1 edge are latched into int0if and int1if at every machine cycle. the values are not actually polled by the circuitry until the next machine cycle. if a re- quest is active and conditions are right for it to be acknowl- edged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. the div itself takes twelve cycles. thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. below shows interrupt response timings. figure 19-7 interrupt response timing diagram int0if int0 pin int0 interrupt int1if int1 pin int1 interrupt ieds [0e6 h ] edge selection int0 edge select ext. interrupt edge selection ieds address : 0e6 h reset value : 00000000 00: int. disable wwwwww 01: falling 10: rising 11: both int1 edge select 00: int. disable 01: falling 10: rising 11: both register ww interrupt goes active interrupt latched interrupt processing interrupt routine 8 f osc max. 12 f osc
gms81c1102 / gms81c1202 62 jan. 2002 ver 2.0 20. watchdog timer the purpose of the watchdog timer is to detect the mal- function (runaway) of program due to external noise or other causes and return the operation to the normal condi- tion. the watchdog timer has two types of clock source. the first type is an on-chip rc oscillator which does not require any external components. this rc oscillator is sep- arate from the external oscillator of the xin pin. it means that the watchdog timer will run, even if the clock on the xin pin of the device has been stopped, for example, by en- tering the stop mode. the other type is a prescaled system clock. the watchdog timer consists of 7-bit binary counter and the watchdog timer data register. the source clock of wdt is overflow of basic interval timer. when the value of 7-bit binary counter is equal to the lower 7 bits of wdtr, the interrupt request flag is generated. this can be used as wdt interrupt or cpu reset signal in accordance with the bit wdton . note: because the watchdog timer counter is enabled af- ter clearing basic interval timer, after the bit wd- ton set to "1", maximum error of timer is depend on prescaler ratio of basic interval timer. the 7-bit binary counter is cleared by setting wdtcl(bit7 of wdtr) and the wdtcl is cleared automatically after 1 machine cycle. the rc oscillated watchdog timer is activated by setting the bit rcwdt of ckctlr and executing the stop in- struction as shown below. the rc oscillation period is variable according to the tem- perature, v dd and process variations from part to part (ap- proximately, 120~180us). the following equation shows the rc oscillated watchdog timer time-out. t rcwdt =clk rc 2 8 [ wdtr.6~0]+(clk rc 2 8 )/2 where, clk rc = 120~180us in addition, this watchdog timer can be used as a simple 7- bit timer by interrupt wdtif. the interval of watchdog timer interrupt is decided by basic interval timer. interval equation is as below. t wdt = [wdtr.6~0] interval of bit figure 20-1 block diagram of watchdog timer : ldm ckctlr,#3fh ; enable the rc-osc wdt ldm wdtr,#0ffh ; set the wdt period stop ; enter the stop mode nop nop ; rc-osc wdt running : ? 8 ? 16 ? 128 ? 256 ? 512 ? 1024 ? 32 ? 64 0 1 mux 8 3 fxin bitr ( 8-bit ) bts[2:0] internal rc osc basic interval timer interrupt btcl clear watchdog timer bitif 7-bit counter wdtr (8-bit) ofd wdtcl wdton interrupt request cpu reset 1 0 clock control register ckctlr address : ech reset value : -0010111 - wakeup rcwdt wdton btcl bts2 bts1 bts0 - 0x1 xxxx watchdog timer register wdtr address : edh reset value : 01111111 wdtcl 7-bit watchdog counter register overflow detection bit manipulation not available bit manipulation not available stop wakeup rcwdt
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 63 21. power saving mode for applications where power consumption is a critical factor, device provides three kinds of power saving func- tions, stop mode, wake-up timer mode and internal rc- oscillated watchdog timer mode. the power saving function is activated by execution of stop instruction after setting the corresponding bit (wakeup, rcwdt) of ckctlr. table 21-1 shows the status of each power saving mode note: before executing stop instruction, clear all in- terrupt request flag. because if the interrupt re- quest flag is set before stop instruction, the mcu runs as if it doesnt perform stop instruction, even though the stop instruction is completed. so insert two lines to clear all interrupt request flags (irqh, irql) before stop instruction as shown each ex- ample. 21.1 stop mode in the stop mode, the on-chip oscillator is stopped. with the clock frozen, all functions are stopped, but the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port di- rection registers. oscillator stops and the systems internal operations are all held up. ? the states of the ram, registers, and latches valid immediately before the system is put in the stop state are all held. ? the program counter stop the address of the instruction to be executed after the instruction stop which starts the stop operating mode. the stop mode is activated by execution of stop in- struction after setting the bit wakeup and rcwdt of ckctlr to 00. (this register should be written by byte operation. if this register is set by bit manipu- lation instruction, for example set1 or clr1 instruc- tion, it may be undesired operation) in the stop mode of operation, v dd can be reduced to min- imize power consumption. care must be taken, however, to ensure that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal operating level, before the stop mode is terminated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. note: after stop instruction, at least two or more nop instruction should be written ex) ldm ckctlr ,#0 00 0_1110b ldm irqh ,#0 ldm irql ,#0 stop nop nop in the stop operation, the dissipation of the power asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage peripheral stop wake-up timer internal rc-wdt ram retain retain retain control registers retain retain retain i/o ports retain retain retain cpu stop stop stop timer0 stop operation stop oscillation stop oscillation stop prescaler stop ? 2048 only stop internal rc oscillator stop stop oscillation entering condition ckctlr[6,5] 00 1x 01 power saving release source reset, int0, int1 reset, int0, int1, timer0 reset, int0, int1, rc-wdt table 21-1 power saving mode
gms81c1102 / gms81c1202 64 jan. 2002 ver 2.0 level (v dd /v ss ), however, when the input level gets high- er than the power voltage level (by approximately 0.3 to 0.5v), a current begins to flow. therefore, if cutting off the output transistor at an i/o port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. release the stop mode the exit from stop mode is hardware reset or external in- terrupt. reset re-defines all the control registers but does not change the on-chip ram. external interrupts allow both on-chip ram and control registers to retain their val- ues. after releasing stop mode, instruction execution is divid- ed into two ways by i-flag(bit2 of psw). if i-flag = 1, the normal interrupt response takes place. if i- flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vec- tor to interrupt service routine. (refer to figure 21-1) when exit from stop mode by external interrupt, enough oscillation stabilization time is required to normal opera- tion. figure 21-2 shows the timing diagram. when release the stop mode, the basic interval timer is activated on wake-up. it is increased from 00 h until ff h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant prescaler di- vide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and stabilized. by reset, exit from stop mode is shown in figure 21-3. minimizing current consumption in stop mode the stop mode is designed to reduce power consumption. to minimize the current consumption during stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. weak pull-ups on port pins should be turned off, if possible. all inputs should be either as v ss or at v dd (or as close to rail as possible). an intermediate voltage on an input pin causes the input buffer to draw a significant amount of current. figure 21-1 stop releasing flow by interrupts figure 21-2 timing of stop mode release by external interrupt iexx =0 =1 stop instruction stop mode interrupt request stop mode release i-flag =1 interrupt service routine next instruction =0 master interrupt enable bit psw[2] corresponding interrupt enable bit (ienh, ienl) ~ ~ stop mode normal operation oscillator (x in pin) ~ ~ ~ ~ n+1 n n+2 00 01 fe ff 00 01 n-1 n-2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ clear basic interval timer stop instruction execution normal operation stabilization time t st > 20ms internal clock external interrupt bit counter ~ ~
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 65 figure 21-3 timing of stop mode release by reset 21.2 wake-up timer mode in the wake-up timer mode, the on-chip oscillator is not stopped. except the prescaler (only 2048 divided ratio) and timer0, all functions are stopped, but the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port direction registers. the wake-up timer mode is activated by execution of stop instruction after setting the bit wakeup of ckctlr to 1. (this register should be written by byte operation. if this register is set by bit manipulation instruction, for example set1 or clr1 instruction, it may be undesired operation) note: after stop instruction, at least two or more nop in- struction should be written ex) ldm tdr0,#0ffh ldm tm0,#0001_1011b ldm ckctlr,#0100_1110b ldm irqh,#0 ldm irql,#0 stop nop nop in addition, the clock source of timer0 should be select- ed to 2048 divided ratio. otherwise, the wake-up func- tion can not work. and the timer0 can be operated as 16-bit timer with timer1 (refer to timer function). the period of wake-up function is varied by setting the tim- er data register 0, tdr0. release the wake-up timer mode the exit from wake-up timer mode is hardware reset, timer0 overflow or external interrupt. reset re-defines all the control registers but does not change the on-chip ram. external interrupts and timer0 overflow allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. if i- flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vec- tor to interrupt service routine (refer to figure 21-1). when exit from wake-up timer mode by external inter- rupt or timer0 overflow, the oscillation stabilization time is not required to normal operation. because this mode do not stop the on-chip oscillator shown as figure 21-4. figure 21-4 wake-up timer mode releasing by external interrupt or timer0 interrupt ~ ~ stop mode oscillator (x in pin) ~ ~ ~ ~ ~ ~ stop instruction execution stabilization time t st = 64ms @4mhz internal clock internal ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ reset reset time can not be controlled by software wake-up timer mode oscillator (x in pin) ~ ~ stop instruction normal operation normal operation cpu clock request interrupt ~ ~ ~ ~ execution do not need stabilization time (stop the cpu clock) ~ ~
gms81c1102 / gms81c1202 66 jan. 2002 ver 2.0 21.3 internal rc-oscillated watchdog timer mode in the internal rc-oscillated watchdog timer mode, the on-chip oscillator is stopped. but internal rc oscillation circuit is oscillated in this mode. the on-chip ram and control registers are held. the port pins out the values held by their respective port data register, port direction regis- ters. the internal rc-oscillated watchdog timer mode is activated by execution of stop instruction after set- ting the bit wakeup and rcwdt of ckctlr to 01. (this register should be written by byte opera- tion. if this register is set by bit manipulation instruc- tion, for example set1 or clr1 instruction, it may be undesired operation) note: after stop instruction, at least two or more nop in- struction should be written ex) ldm wdtr,#1111_1111b ldm ckctlr,#0010_1110b ldm irqh,#0 ldm irql,#0 stop nop nop release the internal rc-oscillated watchdog timer mode the exit from internal rc-oscillated watchdog timer mode is hardware reset or external interrupt. reset re-de- fines all the control registers but does not change the on- chip ram. external interrupts allow both on-chip ram and control registers to retain their values. if i-flag = 1, the normal interrupt response takes place. in this case, if the bit wdton of ckctlr is set to 0 and the bit wdte of ienh is set to 1, the device will exe- cute the watchdog timer interrupt service routine.(figure 21-5) however, if the bit wdton of ckctlr is set to 1, the device will generate the internal reset signal and execute the reset processing. (figure 21-6) if i-flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vector to interrupt service routine (refer to figure 21-1). when exit from internal rc-oscillated watchdog timer mode by external interrupt, the oscillation stabilization time is required for normal operation. figure 21-5 shows the timing diagram. when release the internal rc-oscil- lated watchdog timer mode, the basic interval timer is ac- tivated on wake-up. it is increased from 00 h until ff h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant pres- caler divide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and stabilized. by reset, exit from internal rc-oscillated watchdog tim- er mode is shown in figure 21-6. figure 21-5 internal rcwdt mode releasing by external interrupt or wdt interrupt ~ ~ rcwdt mode normal operation oscillator (x in pin) ~ ~ ~ ~ n+1 n n+2 00 01 fe ff 00 00 n-1 n-2 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ clear basic interval timer stop instruction execution normal operation stabilization time t st > 20ms internal clock external interrupt bit counter ~ ~ internal rc clock (or wdt interrupt)
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 67 figure 21-6 internal rcwdt mode releasing by reset. figure 21-7 application example of unused input port figure 21-8 application example of unused output port ~ ~ oscillator (x in pin) ~ ~ ~ ~ ~ ~ ~ ~ internal clock internal rc clock ~ ~ stop instruction execution stabilization time t st = 64ms @4mhz internal ~ ~ ~ ~ ~ ~ reset by wdt reset reset rcwdt mode time can not be controlled by software input pin v dd gnd i v dd x weak pull-up current flows v dd internal pull-up input pin i v dd x very weak current flows v dd o o open open i=0 o i=0 o gnd when port is configured as an input, input level should be closed to 0v or 5v to avoid power consumption. output pin gnd i in the left case, much current flows from port to gnd. x on off output pin gnd i in the left case, tr. base current flows from port to gnd. i=0 x off on v dd l on off open gnd v dd l on off to avoid power consumption, there should be low output on off o o v dd o to the port .
gms81c1102 / gms81c1202 68 jan. 2002 ver 2.0 22. reset the reset input is the reset pin, which is the input to a schmitt trigger. a reset in accomplished by holding the reset pin low for at least 8 oscillator periods, while the oscillator running. after reset, 64ms (at 4 mhz) add with 7 oscillator periods are required to start execution as shown in figure 22-1 . internal ram is not affected by reset. when v dd is turned on, the ram content is indeterminate. therefore, this ram should be initialized before reading or testing it. initial state of each register is shown as table 12-3 . figure 22-1 timing diagram after reset main program oscillator (x in pin) ? ? fffe ffff stabilization time t st = 64ms at 4mhz reset address data 1 2 3 4 5 6 7 ?? start ? ? ? fe ? adl adh op bus bus reset process step ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 69 23. power fail processor the gms81c1202 has an on-chip power fail detection cir- cuitry to immunize against power noise. a configuration register, pfdr, can enable (if clear/programmed) or disa- ble (if set) the power-fail detect circuitry. if v dd falls be- low 3.0~4.0v range for longer than 50 ns, the power fail situation may reset mcu according to pfdm bit of pfdr. as below pfdr register is not implemented on the in-cir- cuit emulator, user can not experiment with it. therefore, after final development of user program, this function may be experimented. note: power fail processor function is not available on 3v operation, because this function will detect power fail all the time . figure 23-1 power fail detector register figure 23-2 example s/w of reset by power fail pfdr address : efh reset value : -----100 - - - - - pfdis pfdm pfs reserved power fail status 0 : normal operate 1 : this bit force to "1" when operation mode 0 : system clock freezing during power fail 1 : mcu will be reset during power fail disable flag 0 : power fail detection enable 1 : power fail detection disable power fail detector register power fail was detected funtion execution initialize ram data pfs =1 no reset vector initialize all ports initialize registers ram clear yes skip the initial routine
gms81c1102 / gms81c1202 70 jan. 2002 ver 2.0 figure 23-3 power fail processor situations internal reset internal reset internal reset v dd v dd v dd pfv dd max pfv dd min pfv dd max pfv dd min pfv dd max pfv dd min 64ms 64ms t < 64ms 64ms when pfdm = 1 v dd v dd pfv dd max pfv dd min pfv dd max pfv dd min when pfdm = 0 system clock system clock
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 71 24. otp programming the gms87c1102/1202 is one-time prom(otp) microcontroller with 2k bytes electrically programmable read only mem- ory for the gms81c1102/1202 system evaluation, first production and fast mass production. to programming the otp device, user must use the universal programmer which is support hynix semiconductor. 24.1 program memory map program memory consists of configuration area and user program memory area. the configuration memory area has two parts (user id & system configuration bits), the areas are shown below in figure 24-1. the device configuration area can be programmed or left unprogrammed to select device configuration such as security bit. ten memory locations (0f50 h ~ 0fe0 h ) are designated as customer id recording locations where the user can store check- sum or other customer identification numbers. this area is not accessible during normal execution but is readable and writable during program / verify. figure 24-1 device configuration area the security definition method is explained below. 1) after writing h to code protect bit in write & verify mode and getting out of write & verify mode, user cannot read out the program code. but if not getting out of write & verify mode (maintaining programming power vpp = 12.75v), user can verify program code. 2) regardless of code protect, user can read out configuration memory (user id and configuration bits) 3) if user knows security (lock) state, user can read code protect bit in the system configuration bits. device 0f50 h 0f50 h 0ff0 h 0ff0 h id config configuration area 0f60 h id 0f70 h id 0f80 h id 0f90 h id 0fa0 h id 0fb0 h id 0fc0 h id 0fd0 h id 0fe0 h id rc configuration register config address : 0ff0h - lock ---- - 0 : allow code read out 1 : prohibit code read out security bit 0 : normal oscillator 1 : external rc oscillator rc option
gms81c1102 / gms81c1202 72 jan. 2002 ver 2.0 figure 24-2 pin assignment table 24-1 pin description in eprom mode pin no. user mode eprom mode pin name pin name description 1 ra4 (an4) a_d4 address input data input/output a12 a4 d4 2 ra5 (an5) a_d5 a13 a5 d5 3 ra6 (an6) a_d6 a14 a6 d6 4 ra7 (an7) a_d7 a15 a7 d7 5 v dd v dd connect to v dd (6.0v) 6 rb0 (avref/an0) ctl0 read/write control address/data control 7 rb2 (int0) ctl1 8 rb4 (pwm/comp) ctl2 9 x in eprom enable high active, latch address in falling edge 10 x out nc no connection 11 reset v pp programming power (0v, 12.75v) 12 v ss v ss connect to v ss (0v) 13 ra0 (ec0) a_d0 address input data input/output a8 a0 d0 14 ra1 (an1) a_d1 a9 a1 d1 15 ra2 (an2) a_d2 a10 a2 d2 16 ra3 (an3) a_d3 a11 a3 d3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v pp a_d0 a_d1 a_d2 a_d3 eprom enable a_d7 a_d6 a_d5 a_d4 ctl2 ctl1 ctl0 nc v ss v dd gms87c1102
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 73 figure 24-3 pin assignment table 24-2 pin description in eprom mode v dd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v pp a_d0 a_d1 a_d2 a_d3 eprom enable a_d7 a_d6 a_d5 a_d4 ctl2 ctl1 ctl0 v ss nc GMS87C1202 pin no. user mode eprom mode pin name pin name description 1 ra4 (an4) a_d4 address input data input/output a12 a4 d4 2 ra5 (an5) a_d5 a13 a5 d5 3 ra6 (an6) a_d6 a14 a6 d6 4 ra7 (an7) a_d7 a15 a7 d7 5 v dd v dd connect to v dd (6.0v) 6 rb0 (avref/an0) ctl0 read/write control address/data control 7 rb1 (buz) ctl1 8 rb2 (int0) ctl2 9 rb3 (int1) v dd connect to v dd (6.0v) 10 rb4 (pwm/comp) v dd connect to v dd (6.0v) 11 x in eprom enable high active, latch address in falling edge 12 x out nc no connection 13 reset v pp programming power (0v, 12.75v) 14 v ss v ss connect to v ss (0v) 15,16 rc0, 1 v dd connect to v dd (6.0v) 17 ra0 (ec0) a_d0 address input data input/output a8 a0 d0 18 ra1 (an1) a_d1 a9 a1 d1 19 ra2 (an2) a_d2 a10 a2 d2 20 ra3 (an3) a_d3 a11 a3 d3
gms81c1102 / gms81c1202 74 jan. 2002 ver 2.0 figure 24-4 timing diagram in program (write & verify) mode figure 24-5 timing diagram in read mode v pp ctl0 ~ ~ high 8bit ha la data in data ~ ~ ~ ~ ~ ~ ~ ~ out la data in data out eprom enable ctl1 ctl2 a_d7~ v dd v dd1h 0v 0v 0v address input low 8bit address input write mode verify low 8bit address input write mode verify a_d0 t vdds t vppr t vpps ~ ~ v dd1h v dd1h v ihp ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t hld1 t hld2 t set1 t dly1 t dly2 t cd1 t cd1 t cd1 t cd1 v pp ctl0 high 8bit ha la data la data data eprom enable ctl1 ctl2 a_d7~ v dd v dd2h 0v 0v 0v address input low 8bit address input data a_d0 t vdds t vppr t vpps v dd2h v dd2h v ihp t hld1 t hld2 t set1 t dly1 t dly2 t cd1 t cd2 t cd2 t cd1 ha la output low 8bit address input high 8bit address input low 8bit address input data output data output after input a high address, output data following low address input anothe high address step
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 75 table 24-3 ac/dc requirements for program/read mode parameter symbol min typ max unit programming supply current i vpp --50ma supply current in eprom mode i vddp --20ma v pp level during programming v ihp 12.0 12.5 13.0 v v dd level in program mode v dd1h 566.5v v dd level in read mode v dd2h -2.7-v ctl2~0 high level in eprom mode v ihc 0.8v dd --v ctl2~0 low level in eprom mode v ilc -- 0.2v dd v a_d7~a_d0 high level in eprom mode v ihad 0.9v dd --v a_d7~a_d0 low level in eprom mode v ilad -- 0.1v dd v v dd saturation time t vdds 1- -ms v pp setup time t vppr --1ms v pp saturation time t vpps 1- -ms eprom enable setup time after data input t set1 200 ns eprom enable hold time after t set1 t hld1 500 ns eprom enable delay time after t hld1 t dly1 200 ns eprom enable hold time in write mode t hld2 100 ns eprom enable delay time after t hld2 t dly2 200 ns ctl2,1 setup time after low address input and data input t cd1 100 ns ctl1 setup time before data output in read and verify mode t cd2 100 ns
gms81c1102 / gms81c1202 76 jan. 2002 ver 2.0 figure 24-6 programming flow chart start set v dd =v dd1h set v pp =v ihp verify blank first address location eprom write n=1 verify pass last address apply 3n program cycle 100us program time next address location n > 25 report programming failure report programming failure verify fof all address verify ok report verify failure report programming ok v dd =v pp =0v end no yes yes yes yes yes no no no no
gms81c1102 / gms81c1202 jan. 2002 ver 2.0 77 figure 24-7 reading flow chart start set v dd =v dd2h set v pp =v ihp last address first address location v dd =0v report read ok v pp =0v next address location verify fof all address end no yes
gms81c1102 / gms81c1202 78 jan. 2002 ver 2.0
appendix
gms81c1102/gms81c1202 jan. 2002 ver 2.0 i appendix a. instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das 111 ei ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa 111 beq rel sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
gms81c1102/gms81c1202 ii jan. 2002 ver 2.0 b. instruction set 1. arithmetic/ logic operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. 2 adc dp 05 2 3 a ? ( a ) + ( m ) + c 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 nv--h-zc 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8 adc { x } 14 1 3 9 and #imm 84 2 2 logical and 10 and dp 85 2 3 a ? ( a ) ( m ) 11 and dp + x 86 2 4 12 and !abs 87 3 4 n-----z- 13 and !abs + y 95 3 5 14 and [ dp + x ] 96 2 6 15 and [ dp ] + y 97 2 6 16 and { x } 94 1 3 17 asl a 08 1 2 arithmetic shift left 18 asl dp 09 2 4 n-----zc 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 44 2 2 compare accumulator contents with memory contents 22 cmp dp 45 2 3 ( a ) - ( m ) 23 cmp dp + x 46 2 4 24 cmp !abs 47 3 4 n-----zc 25 cmp !abs + y 55 3 5 26 cmp [ dp + x ] 56 2 6 27 cmp [ dp ] + y 57 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents 30 cmpx dp 6c 2 3 ( x ) - ( m ) n-----zc 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents 33 cmpy dp 8c 2 3 ( y ) - ( m ) n-----zc 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1s complement : ( dp ) ? ~( dp ) n-----z- 36 daa df 1 3 decimal adjust for addition n-----zc 37 das cf 1 3 decimal adjust for subtraction n-----zc 38 dec a a8 1 2 decrement n-----z- 39 dec dp a9 2 4 m ? ( m ) - 1 40 dec dp + x b9 2 5 n-----z- 41 dec !abs b8 3 5 42 dec x af 1 2 43 dec y be 1 2 44 div 9b 1 12 divide : ya / x q: a, r: y nv--h-z- 0 0 c 7654321
gms81c1102/gms81c1202 jan. 2002 ver 2.0 iii no. mnemonic op code byte no cycle no operation flag nvgbhizc 45 eor #imm a4 2 2 exclusive or 46 eor dp a5 2 3 a ? ( a ) ? ( m ) 47 eor dp + x a6 2 4 48 eor !abs a7 3 4 n-----z- 49 eor !abs + y b5 3 5 50 eor [ dp + x ] b6 2 6 51 eor [ dp ] + y b7 2 6 52 eor { x } b4 1 3 53 inc a 88 1 2 increment n-----z- 54 inc dp 89 2 4 m ? ( m ) + 1 55 inc dp + x 99 2 5 n-----z- 56 inc !abs 98 3 5 57 inc x 8f 1 2 58 inc y 9e 1 2 59 lsr a 48 1 2 logical shift right 60 lsr dp 49 2 4 n-----zc 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y a n-----z- 64 or #imm 64 2 2 logical or 65 or dp 65 2 3 a ? ( a ) ( m ) 66 or dp + x 66 2 4 67 or !abs 67 3 4 n-----z- 68 or !abs + y 75 3 5 69 or [ dp + x ] 76 2 6 70 or [ dp ] + y 77 2 6 71 or { x } 74 1 3 72 rol a 28 1 2 rotate left through carry 73 rol dp 29 2 4 n-----zc 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry 77 ror dp 69 2 4 n-----zc 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 24 2 2 subtract with carry 81 sbc dp 25 2 3 a ? ( a ) - ( m ) - ~( c ) 82 sbc dp + x 26 2 4 83 sbc !abs 27 3 4 nv--hzc 84 sbc !abs + y 35 3 5 85 sbc [ dp + x ] 36 2 6 86 sbc [ dp ] + y 37 2 6 87 sbc { x } 34 1 3 88 tst dp 4c 2 3 test memory contents for negative or zero ( dp ) - 00 h n-----z- 89 xcn ce 1 5 exchange nibbles within the accumulator a 7 ~a 4 ? a 3 ~a 0 n-----z- 0 0 c 7654321 0 c 7654321 0c 7654321
gms81c1102/gms81c1202 iv jan. 2002 ver 2.0 2. register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c4 2 2 load accumulator 2 lda dp c5 2 3 a ? ( m ) 3 lda dp + x c6 2 4 4 lda !abs c7 3 4 5 lda !abs + y d5 3 5 n-----z- 6 lda [ dp + x ] d6 2 6 7 lda [ dp ] + y d7 2 6 8 lda { x } d4 1 3 9 lda { x }+ db 1 4 x- register auto-increment : a ? ( m ) , x ? x + 1 10 ldm dp,#imm e4 3 5 load memory with immediate data : ( m ) ? imm -------- 11 ldx #imm 1e 2 2 load x-register 12 ldx dp cc 2 3 x ? ( m ) n-----z- 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y-register 16 ldy dp c9 2 3 y ? ( m ) n-----z- 17 ldy dp + x d9 2 4 18 ldy !abs d8 3 4 19 sta dp e5 2 4 store accumulator contents in memory 20 sta dp + x e6 2 5 ( m ) ? a 21 sta !abs e7 3 5 22 sta !abs + y f5 3 6 -------- 23 sta [ dp + x ] f6 2 7 24 sta [ dp ] + y f7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x- register auto-increment : ( m ) ? a, x ? x + 1 27 stx dp ec 2 4 store x-register contents in memory 28 stx dp + y ed 2 5 ( m ) ? x -------- 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y-register contents in memory 31 sty dp + x f9 2 5 ( m ) ? y -------- 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x-register : x ? a n-----z- 34 tay 9f 1 2 transfer accumulator contents to y-register : y ? a n-----z- 35 tspx ae 1 2 transfer stack-pointer contents to x-register : x ? sp n-----z- 36 txa c8 1 2 transfer x-register contents to accumulator: a ? x n-----z- 37 txsp 8e 1 2 transfer x-register contents to stack-pointer: sp ? x n-----z- 38 tya bf 1 2 transfer y-register contents to accumulator: a ? y n-----z- 39 xax ee 1 4 exchange x-register contents with accumulator :x ? a -------- 40 xay de 1 4 exchange y-register contents with accumulator :y ? a -------- 41 xma dp bc 2 5 exchange memory contents with accumulator 42 xma dp+x ad 2 6 ( m ) ? a n-----z- 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x-register contents with y-register : x ? y --------
gms81c1102/gms81c1202 jan. 2002 ver 2.0 v 3. 16-bit operation 4. bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16-bits add without carry ya ? ( ya ) + ( dp +1 ) ( dp ) nv--h-zc 2 cmpw dp 5d 2 4 compare ya contents with memory pair contents : (ya) - (dp+1)(dp) n-----zc 3decw dp bd 2 6 decrement memory pair ( dp+1)( dp) ? ( dp+1) ( dp) - 1 n-----z- 4 incw dp 9d 2 6 increment memory pair ( dp+1) ( dp) ? ( dp+1) ( dp ) + 1 n-----z- 5 ldya dp 7d 2 5 load ya ya ? ( dp +1 ) ( dp ) n-----z- 6 stya dp dd 2 5 store ya ( dp +1 ) ( dp ) ? ya -------- 7 subw dp 3d 2 5 16-bits substact without carry ya ? ( ya ) - ( dp +1) ( dp) nv--h-zc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c-flag : c ? ( c ) ( m .bit ) -------c 2 and1b m.bit 8b 3 4 bit and c-flag and not : c ? ( c ) ~( m .bit ) -------c 3 bit dp 0c 2 4 bit test a with memory : mm----z- 4 bit !abs 1c 3 5 z ? ( a ) ( m ) , n ? ( m 7 ) , v ? ( m 6 ) 5 clr1 dp.bit y1 2 4 clear bit : ( m.bit ) ? 0 -------- 6 clra1 a.bit 2b 2 2 clear a bit : ( a.bit ) ? 0 -------- 7 clrc 20 1 2 clear c-flag : c ? 0 -------0 8 clrg 40 1 2 clear g-flag : g ? 0 --0----- 9 clrv 80 1 2 clear v-flag : v ? 0 -0--0--- 10 eor1 m.bit ab 3 5 bit exclusive-or c-flag : c ? ( c ) ? ( m .bit ) -------c 11 eor1b m.bit ab 3 5 bit exclusive-or c-flag and not : c ? ( c ) ? ~(m .bit) -------c 12 ldc m.bit cb 3 4 load c-flag : c ? ( m .bit ) -------c 13 ldcb m.bit cb 3 4 load c-flag with not : c ? ~( m .bit ) -------c 14 not1 m.bit 4b 3 5 bit complement : ( m .bit ) ? ~( m .bit ) -------- 15 or1 m.bit 6b 3 5 bit or c-flag : c ? ( c ) ( m .bit ) -------c 16 or1b m.bit 6b 3 5 bit or c-flag and not : c ? ( c ) ~( m .bit ) -------c 17 set1 dp.bit x1 2 4 set bit : ( m.bit ) ? 1 -------- 18 seta1 a.bit 0b 2 2 set a bit : ( a.bit ) ? 1 -------- 19 setc a0 1 2 set c-flag : c ? 1 -------1 20 setg c0 1 2 set g-flag : g ? 1 --1----- 21 stc m.bit eb 3 6 store c-flag : ( m .bit ) ? c -------- 22 tclr1 !abs 5c 3 6 test and clear bits with a : a - ( m ) , ( m ) ? ( m ) ~( a ) n-----z- 23 tset1 !abs 3c 3 6 test and set bits with a : a - ( m ) , ( m ) ? ( m ) ( a ) n-----z-
gms81c1102/gms81c1202 vi jan. 2002 ver 2.0 5. branch / jump operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a.bit,rel y2 2 4/6 branch if bit clear : -------- 2 bbc dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ? ( pc ) + rel 3 bbs a.bit,rel x2 2 4/6 branch if bit set : -------- 4 bbs dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ? ( pc ) + rel 5 bcc rel 50 2 2/4 branch if carry bit clear if ( c ) = 0 , then pc ? ( pc ) + rel -------- 6 bcs rel d0 2 2/4 branch if carry bit set if ( c ) = 1 , then pc ? ( pc ) + rel -------- 7 beq rel f0 2 2/4 branch if equal if ( z ) = 1 , then pc ? ( pc ) + rel -------- 8 bmi rel 90 2 2/4 branch if minus if ( n ) = 1 , then pc ? ( pc ) + rel -------- 9 bne rel 70 2 2/4 branch if not equal if ( z ) = 0 , then pc ? ( pc ) + rel -------- 10 bpl rel 10 2 2/4 branch if minus if ( n ) = 0 , then pc ? ( pc ) + rel -------- 11 bra rel 2f 2 4 branch always pc ? ( pc ) + rel -------- 12 bvc rel 30 2 2/4 branch if overflow bit clear if (v) = 0 , then pc ? ( pc) + rel -------- 13 bvs rel b0 2 2/4 branch if overflow bit set if (v) = 1 , then pc ? ( pc ) + rel -------- 14 call !abs 3b 3 8 subroutine call 15 call [dp] 5f 2 8 m( sp) ? ( pc h ), sp ? sp - 1, m(sp) ? (pc l ), sp ? sp - 1, if !abs, pc ? abs ; if [dp], pc l ? ( dp ), pc h ? ( dp+1 ) . -------- 16 cbne dp,rel fd 3 5/7 compare and branch if not equal : -------- 17 cbne dp+x,rel 8d 3 6/8 if ( a ) 1 ( m ) , then pc ? ( pc ) + rel. 18 dbne dp,rel ac 3 5/7 decrement and branch if not equal : -------- 19 dbne y,rel 7b 2 4/6 if ( m ) 1 0 , then pc ? ( pc ) + rel. 20 jmp !abs 1b 3 3 unconditional jump 21 jmp [!abs] 1f 3 5 pc ? jump address -------- 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u-page call m(sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ), sp ? sp - 1, pc l ? ( upage ), pc h ? 0ff h . -------- 24 tcall n na 1 8 table call : (sp) ? ( pc h ), sp ? sp - 1, m(sp) ? ( pc l ),sp ? sp - 1, pc l ? (table vector l), pc h ? (table vector h) --------
gms81c1102/gms81c1202 jan. 2002 ver 2.0 vii 6. control operation & etc. no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 brk 0f 1 8 software interrupt : b ? 1, m(sp) ? (pc h ), sp ? sp-1, m(s) ? (pc l ), sp ? sp - 1, m(sp) ? (psw), sp ? sp -1, pc l ? ( 0ffde h ) , pc h ? ( 0ffdf h ) . ---1-0-- 2 di 60 1 3 disable interrupts : i ? 0 -----0-- 3 ei e0 1 3 enable interrupts : i ? 1 -----1-- 4 nop ff 1 2 no operation -------- 5 pop a 0d 1 4 sp ? sp + 1, a ? m( sp ) 6 pop x 2d 1 4 sp ? sp + 1, x ? m( sp ) -------- 7 pop y 4d 1 4 sp ? sp + 1, y ? m( sp ) 8 pop psw 6d 1 4 sp ? sp + 1, psw ? m( sp ) restored 9 push a 0e 1 4 m( sp ) ? a , sp ? sp - 1 10 push x 2e 1 4 m( sp ) ? x , sp ? sp - 1 -------- 11 push y 4e 1 4 m( sp ) ? y , sp ? sp - 1 12 push psw 6e 1 4 m( sp ) ? psw , sp ? sp - 1 13 ret 6f 1 5 return from subroutine sp ? sp +1, pc l ? m( sp ), sp ? sp +1, pc h ? m( sp ) -------- 14 reti 7f 1 6 return from interrupt sp ? sp +1, psw ? m( sp ), sp ? sp + 1, pc l ? m( sp ), sp ? sp + 1, pc h ? m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) --------

▲Up To Search▲

Price & Availability of GMS87C1202

	To Download GMS87C1202 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .